mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-31 09:44:27 +02:00
6 lines
74 B
Verilog
6 lines
74 B
Verilog
|
module top;
|
||
|
|
wire x, y;
|
||
|
|
assign y = 1;
|
||
|
|
assign x = ~y;
|
||
|
|
endmodule
|