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13 lines
376 B
Verilog
13 lines
376 B
Verilog
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module mod(
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input input_a, input_b,
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input [1:0] input_c,
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input [5:0] input_d,
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output [1:0] output_a, output_b,
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output [5:0] output_c, output_d
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);
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and gate_a[1:0] (output_a, input_a, input_c);
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and gate_b[1:0] (output_b, input_a, input_b);
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and gate_c[5:0] (output_c, input_a, input_d);
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and gate_d[5:0] (output_d, input_b, input_d);
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endmodule
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