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13 lines
315 B
Verilog
13 lines
315 B
Verilog
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module top;
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wire [31:0] a1;
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wire [7:0] a2;
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if (1) begin : blk
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wire [31:0] b1;
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wire [7:0] b2;
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initial $display("b1 %b %b", b1, 1);
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initial $display("b2 %b %b", b2, 1);
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end
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initial $display("a1 %b %b", a1, 2);
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initial $display("a2 %b %b", a2, 8'sd2);
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endmodule
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