mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-30 01:18:10 +02:00
9 lines
173 B
Verilog
9 lines
173 B
Verilog
|
module Module(input clock, input clear, input data);
|
||
|
|
wire x, y;
|
||
|
|
assign y = data;
|
||
|
|
assign x = y;
|
||
|
|
task hello;
|
||
|
|
$display("Hello!");
|
||
|
|
endtask
|
||
|
|
endmodule
|