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11 lines
245 B
Systemverilog
11 lines
245 B
Systemverilog
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module other;
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parameter STR = "missing";
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initial $display("other: STR=%s $bits(STR)=%0d", STR, $bits(STR));
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endmodule
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module mod;
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parameter STR = "missing";
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initial $display("mod: STR=%s", STR);
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other #("HI") m();
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endmodule
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