Files

24 lines
405 B
Systemverilog
Raw Permalink Normal View History

2020-12-08 11:28:28 -07:00
module Example(
input a, b,
(* who=1 *) output c,
(* what=2 *) output d, e,
input f,
(* when=3 *) (* where=4 *) output g, h, i
);
endmodule
(* a=1 *) module top;
2020-12-08 11:28:28 -07:00
(* foo="bar" *) reg x;
initial begin
2021-07-09 10:34:35 -04:00
(* bar = "baz" *) x = 1;
$display(x);
end
2020-12-08 11:28:28 -07:00
reg a, b;
wire c;
wire d, e;
reg f;
wire g, h, i;
Example m(a,b,c,d,e,f,g,h,i);
endmodule