Port util-logic

This commit is contained in:
Eugene Yokota 2021-12-20 02:59:03 -05:00
parent cd43045444
commit 4bbecf4ee9
2 changed files with 3 additions and 2 deletions

View File

@ -187,6 +187,7 @@ lazy val sbtRoot: Project = (project in file("."))
utilLogging,
utilControl,
completeProj,
logicProj,
)
.settings(
minimalSettings,

View File

@ -98,7 +98,7 @@ object Formula {
assert(literals.nonEmpty, "'And' requires at least one literal.")
}
final case object True extends Formula
case object True extends Formula
}
@ -162,7 +162,7 @@ object Logic {
private[this] def graph(deps: Map[Atom, Set[Literal]]) = new Dag.DirectedSignedGraph[Atom] {
type Arrow = Literal
def nodes = deps.keys.toList
def nodes: List[Atom] = deps.keys.toList
def dependencies(a: Atom) = deps.getOrElse(a, Set.empty).toList
def isNegative(b: Literal) = b match {