mirror of https://github.com/openXC7/prjxray.git
441 lines
11 KiB
Python
441 lines
11 KiB
Python
import random
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random.seed(0)
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import os
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import re
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def slice_xy():
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'''Return (X1, X2), (Y1, Y2) from XRAY_ROI, exclusive end (for xrange)'''
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# SLICE_X12Y100:SLICE_X27Y149
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# Note XRAY_ROI_GRID_* is something else
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m = re.match(r'SLICE_X(.*)Y(.*):SLICE_X(.*)Y(.*)', os.getenv('XRAY_ROI'))
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ms = [int(m.group(i + 1)) for i in range(4)]
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return ((ms[0], ms[2] + 1), (ms[1], ms[3] + 1))
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CLBN = 4
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SLICEX, SLICEY = slice_xy()
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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print('//SLICEX: %s' % str(SLICEX))
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print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested CLBs: %s' % str(CLBN))
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# Rearranged to sweep Y so that carry logic is easy to allocate
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# XXX: careful...if odd number of Y in ROI will break carry
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def gen_slicems():
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'''
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SLICEM at the following:
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SLICE_XxY*
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Where Y any value
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x
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Always even (ie 100, 102, 104, etc)
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In our ROI
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x = 6, 8, 10, 12, 14
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'''
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# TODO: generate this from DB
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assert((12, 28) == SLICEX)
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for slicex in (12, 14):
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for slicey in range(*SLICEY):
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# caller may reject position if needs more room
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#yield ("SLICE_X%dY%d" % (slicex, slicey), (slicex, slicey))
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yield "SLICE_X%dY%d" % (slicex, slicey)
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DIN_N = CLBN * 8
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DOUT_N = CLBN * 8
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print('''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = %d;
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localparam integer DOUT_N = %d;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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''' % (DIN_N, DOUT_N))
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f = open('params.csv', 'w')
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f.write('module,loc,n,def_a\n')
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slices = gen_slicems()
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print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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bel = ''
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# Can fit 4 per CLB
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# BELable
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multi_bels_by = [
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'SRL16E',
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'SRLC32E',
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]
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# Not BELable
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multi_bels_bn = [
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'RAM32X1S',
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'RAM64X1S',
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]
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# Those requiring special resources
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# Just make one per module
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greedy_modules = [
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'my_RAM128X1D',
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'my_RAM128X1S',
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'my_RAM256X1S',
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]
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loc = next(slices)
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cparams = ''
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# Multi module
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if random.randint(0, 3) > 0:
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params = ''
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module = 'my_ram_N'
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# Pick one un-LOCable and then fill in with LOCable
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unbel_beli = random.randint(0, 3)
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bels = []
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for beli in range(4):
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belc = chr(ord('A') + beli)
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if beli == unbel_beli:
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# Chose a BEL instance that will get implicitly placed
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bel = random.choice(multi_bels_bn)
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params += ', .N_%s(1)' % bel
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else:
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bel = random.choice(multi_bels_by)
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params += ', .%c_%s(1)' % (belc, bel)
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bels.append(bel)
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# Record the BELs we chose in the module (A, B, C, D)
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cparams = ',' + (', '.join(bels))
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# Greedy module
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# Don't place anything else in it
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# For solving muxes vs previous results
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else:
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module = random.choice(greedy_modules)
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params = ''
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print(' %s' % module)
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print(' #(.LOC("%s")%s)' % (loc, params))
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print(' clb_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));' % (i, 8 * i, 8 * i))
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f.write('%s,%s%s\n' % (module, loc, cparams))
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f.close()
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print('''endmodule
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// ---------------------------------------------------------------------
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''')
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print('''
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//***************************************************************
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//Supermodule
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//BEL: yes
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module my_ram_N (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter D_SRL16E=0;
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parameter D_SRLC32E=0;
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parameter C_SRL16E=0;
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parameter C_SRLC32E=0;
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parameter B_SRL16E=0;
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parameter B_SRLC32E=0;
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parameter A_SRL16E=0;
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parameter A_SRLC32E=0;
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parameter N_RAM32X1S=0;
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parameter N_RAM64X1S=0;
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generate
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if (D_SRL16E) begin
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(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
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SRL16E #(
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) lutd (
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.Q(dout[3]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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end
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if (D_SRLC32E) begin
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(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutd (
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.Q(dout[3]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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end
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if (C_SRL16E) begin
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(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
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SRL16E #(
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) lutc (
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.Q(dout[2]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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end
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if (C_SRLC32E) begin
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(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutc (
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.Q(dout[2]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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end
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if (B_SRL16E) begin
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(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
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SRL16E #(
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) lutb (
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.Q(dout[1]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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end
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if (B_SRLC32E) begin
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(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[1]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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end
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if (A_SRL16E) begin
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(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
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SRL16E #(
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) luta (
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.Q(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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end
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if (A_SRLC32E) begin
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(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[0]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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end
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if (N_RAM32X1S) begin
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM32X1S #(
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) RAM32X1S (
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.O(dout[4]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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end
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if (N_RAM64X1S) begin
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM64X1S #(
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) RAM64X1S (
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.O(dout[4]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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end
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endgenerate
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endmodule
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//***************************************************************
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//Basic
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//BEL: yes
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module my_SRL16E (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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SRL16E #(
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) SRL16E (
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.Q(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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endmodule
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//BEL: yes
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module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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wire mc31c;
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lut (
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.Q(dout[0]),
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.Q31(mc31c),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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endmodule
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//BEL: can't
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module my_RAM32X1S (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM32X1S #(
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) RAM32X1S (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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endmodule
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//BEL: can't
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module my_RAM64X1S (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM64X1S #(
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) RAM64X1S (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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//***************************************************************
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//WA*USED
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//Dedicated LOC
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module my_RAM128X1D (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM128X1D #(
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.INIT(128'h0),
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.IS_WCLK_INVERTED(1'b0)
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) RAM128X1D (
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.DPO(dout[0]),
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.SPO(dout[1]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[2]));
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endmodule
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//Dedicated LOC
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module my_RAM128X1S (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM128X1S #(
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) RAM128X1S (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.A6(din[6]),
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.D(din[7]),
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.WCLK(din[0]),
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.WE(din[1]));
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endmodule
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//Dedicated LOC
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module my_RAM256X1S (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM256X1S #(
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) RAM256X1S (
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.O(dout[0]),
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.A({din[0], din[7:0]}),
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.D(din[0]),
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.WCLK(din[1]),
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.WE(din[2]));
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endmodule
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''')
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