mirror of https://github.com/openXC7/prjxray.git
106 lines
3.5 KiB
Python
Executable File
106 lines
3.5 KiB
Python
Executable File
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import argparse
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from migen import *
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from litex.boards.platforms import arty
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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# # #
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pll_clkin = Signal()
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self.specials += Instance(
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"BUFG", i_I=platform.request("clk100"), o_O=pll_clkin)
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(pll_clkin, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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class MinSoC(SoCSDRAM):
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def __init__(
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self, sys_clk_freq=int(50e6), integrated_rom_size=0x8000,
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**kwargs):
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platform = arty.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(
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self,
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platform,
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clk_freq=sys_clk_freq,
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integrated_rom_size=integrated_rom_size,
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integrated_sram_size=0x8000,
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cpu_variant="lite",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
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platform.request("ddram"),
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memtype="DDR3",
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nphases=4,
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sys_clk_freq=sys_clk_freq)
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self.add_csr("ddrphy")
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sdram_module = MT41K128M16(sys_clk_freq, "1:4")
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self.register_sdram(
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self.ddrphy,
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geom_settings=sdram_module.geom_settings,
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timing_settings=sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
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builder_args(parser)
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soc_sdram_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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cls = MinSoC
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soc = cls(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args))
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if __name__ == "__main__":
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main()
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