mirror of https://github.com/openXC7/prjxray.git
81 lines
2.1 KiB
Python
Executable File
81 lines
2.1 KiB
Python
Executable File
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import argparse
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from migen import *
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from litex.boards.platforms import arty
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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self.cd_sys.clk.attr.add("keep")
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll_clkin = Signal()
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pll.register_clkin(pll_clkin, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += Instance(
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"BUFG", i_I=platform.request("clk100"), o_O=pll_clkin)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(
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self, sys_clk_freq=int(50e6), integrated_rom_size=0x8000,
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**kwargs):
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platform = arty.Platform()
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SoCCore.__init__(
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self,
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platform,
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clk_freq=sys_clk_freq,
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integrated_rom_size=integrated_rom_size,
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integrated_sram_size=0x8000,
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ident="MiniLitex",
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cpu_variant="lite",
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**kwargs)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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cls = BaseSoC
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soc = cls(**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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