mirror of https://github.com/openXC7/prjxray.git
29 lines
1.3 KiB
Tcl
29 lines
1.3 KiB
Tcl
create_project -force -name top -part $::env(XRAY_PART)
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set_msg_config -id {Common 17-55} -new_severity {Warning}
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read_verilog ../../verilog/VexRiscv_Lite.v
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read_verilog ../../verilog/top.v
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read_xdc ../top.xdc
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synth_design -directive default -top top -part $::env(XRAY_PART)
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report_timing_summary -file top_timing_synth.rpt
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report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
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report_utilization -file top_utilization_synth.rpt
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opt_design -directive default
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place_design -directive default
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report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
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report_utilization -file top_utilization_place.rpt
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report_io -file top_io.rpt
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report_control_sets -verbose -file top_control_sets.rpt
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report_clock_utilization -file top_clock_utilization.rpt
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route_design -directive default
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phys_opt_design -directive default
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report_timing_summary -no_header -no_detailed_paths
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write_checkpoint -force top_route.dcp
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report_route_status -file top_route_status.rpt
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report_drc -file top_drc.rpt
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report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
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report_power -file top_power.rpt
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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write_bitstream -force top.bit
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write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
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quit
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