mirror of https://github.com/openXC7/prjxray.git
87 lines
3.1 KiB
Tcl
87 lines
3.1 KiB
Tcl
create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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# write_bitstream -force design.bit
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proc print_tile_pair {fp t1 t2} {
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set t1 [get_tiles $t1]
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set t2 [get_tiles $t2]
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puts "Checking $t1 against $t2."
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set t1_nodes [lsort -unique [get_nodes -quiet -of_objects [get_wires -of_objects $t1]]]
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set t2_nodes [lsort -unique [get_nodes -quiet -of_objects [get_wires -of_objects $t2]]]
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set nodes {}
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foreach node $t1_nodes {
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if {$node in $t2_nodes} {
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lappend nodes $node
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}
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}
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foreach node $nodes {
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set t1_wires [get_wires -quiet -filter "TILE_NAME == $t1" -of_objects $node]
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set t2_wires [get_wires -quiet -filter "TILE_NAME == $t2" -of_objects $node]
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foreach w1 $t1_wires {
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foreach w2 $t2_wires {
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puts $fp "$w1 $w2"
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}
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}
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}
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}
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proc print_tile_pairs {fp lst} {
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for {set i 1} {$i < [llength $lst]} {incr i} {
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print_tile_pair $fp [lindex $lst [expr $i - 1]] [lindex $lst $i]
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}
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}
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set fp [open "tilepairs.txt" w]
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if {$::env(XRAY_DATABASE) == "artix7"} {
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# horizontal pairs
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print_tile_pairs $fp "INT_R_X13Y114 CLBLL_R_X13Y114 CLBLL_L_X14Y114 INT_L_X14Y114 INT_R_X15Y114"
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print_tile_pairs $fp "VBRK_X29Y125 CLBLM_L_X10Y120 INT_L_X10Y120 INT_R_X11Y120 CLBLM_R_X11Y120 VBRK_X34Y125 CLBLL_L_X12Y120"
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print_tile_pairs $fp "CLBLL_R_X17Y113 VFRAME_X47Y118"
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print_tile_pairs $fp "HCLK_VBRK_X29Y130 HCLK_CLB_X30Y130 HCLK_L_X31Y130 HCLK_R_X32Y130 HCLK_CLB_X33Y130 HCLK_VBRK_X34Y130 HCLK_CLB_X35Y130"
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print_tile_pairs $fp "HCLK_CLB_X46Y130 HCLK_VFRAME_X47Y130"
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print_tile_pairs $fp "T_TERM_INT_X31Y156 T_TERM_INT_X32Y156"
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print_tile_pairs $fp "BRKH_CLB_X10Y99 BRKH_INT_X10Y99 BRKH_INT_X11Y99 BRKH_CLB_X11Y99"
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print_tile_pairs $fp "BRKH_B_TERM_INT_X36Y104 BRKH_B_TERM_INT_X37Y104"
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# vertical pairs
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print_tile_pairs $fp "CLBLM_L_X10Y115 CLBLM_L_X10Y114"
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print_tile_pairs $fp "INT_L_X10Y115 INT_L_X10Y114"
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print_tile_pairs $fp "INT_R_X11Y115 INT_R_X11Y114"
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print_tile_pairs $fp "CLBLM_R_X11Y115 CLBLM_R_X11Y114"
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print_tile_pairs $fp "VBRK_X34Y120 VBRK_X34Y119"
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print_tile_pairs $fp "CLBLL_L_X12Y115 CLBLL_L_X12Y114"
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print_tile_pairs $fp "CLBLL_R_X13Y115 CLBLL_R_X13Y115"
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print_tile_pairs $fp "VFRAME_X47Y120 VFRAME_X47Y119"
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print_tile_pairs $fp "T_TERM_INT_X31Y156 INT_L_X10Y149"
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print_tile_pairs $fp "T_TERM_INT_X32Y156 INT_R_X11Y149"
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print_tile_pairs $fp "CLBLM_L_X10Y100 BRKH_CLB_X10Y99"
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print_tile_pairs $fp "INT_L_X10Y100 BRKH_INT_X10Y99"
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print_tile_pairs $fp "INT_R_X11Y100 BRKH_INT_X11Y99"
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print_tile_pairs $fp "CLBLM_R_X11Y100 BRKH_CLB_X11Y99"
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print_tile_pairs $fp "INT_L_X12Y100 BRKH_B_TERM_INT_X36Y104"
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print_tile_pairs $fp "INT_R_X13Y100 BRKH_B_TERM_INT_X37Y104"
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}
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close $fp
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