mirror of https://github.com/openXC7/prjxray.git
94 lines
2.5 KiB
Python
94 lines
2.5 KiB
Python
#!/usr/bin/env python3
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# FIXME: getting two bits
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# 00_40 31_46
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# Can we find instance where they are not aliased?
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WA7USED = 0
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import sys, re, os
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design.bits")
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# Can fit 4 per CLB
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# BELable
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multi_bels_by = [
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'SRL16E',
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'SRLC32E',
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]
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# Not BELable
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multi_bels_bn = [
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'RAM32X1S',
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'RAM64X1S',
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]
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# Those requiring special resources
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# Just make one per module
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greedy_modules = [
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'my_RAM128X1D',
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'my_RAM128X1S',
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'my_RAM256X1S',
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]
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print("Loading tags")
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'''
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module,loc,bela,belb,belc,beld
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my_ram_N,SLICE_X12Y100,SRL16E,SRLC32E,SRLC32E,SRLC32E
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my_ram_N,SLICE_X12Y101,SRLC32E,SRL16E,SRL16E,SRLC32E
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my_ram_N,SLICE_X12Y102,SRLC32E,SRL16E,SRLC32E,RAM32X1S
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my_RAM256X1S,SLICE_X12Y103,,,,
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'''
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f = open('params.csv', 'r')
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f.readline()
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for l in f:
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l = l.strip()
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module,loc,bela,belb,belc,beld = l.split(',')
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bels = [bela,belb,belc,beld]
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if module in greedy_modules:
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'''
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my_RAM128X1D #(.LOC("SLICE_X12Y100"))
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WA7USED
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my_RAM128X1S #(.LOC("SLICE_X12Y102"))
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WA7USED
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my_RAM256X1S #(.LOC("SLICE_X12Y103"))
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WA7USED, WA8USED
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'''
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which = 'D'
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WA7USED and segmk.addtag(loc, "WA7USED", 1)
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segmk.addtag(loc, "WA8USED", module == 'my_RAM256X1S')
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else:
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'''
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LUTD
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01_23 01_59 30_47 31_47
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SRL16E 1 1 1
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SRLC32E 1 1
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RAM32X1S 1 1 1
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RAM64X1S 1 1
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01_23: WEMUX.CE (more info needed)
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01_59: half sized memory
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30_47: SRL mode
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31_47: RAM mode
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'''
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for which, bel in zip('ABCD', bels):
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segmk.addtag(loc, "%sLUT.SMALL" % which, bel in ('SRL16E', 'RAM32X1S'))
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segmk.addtag(loc, "%sLUT.SRL" % which, bel in ('SRL16E', 'SRLC32E'))
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# Only valid in D
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if which == 'D':
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segmk.addtag(loc, "%sLUT.RAM" % which, bel in ('RAM32X1S', 'RAM64X1S'))
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WA7USED and segmk.addtag(loc, "WA7USED", 0)
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segmk.addtag(loc, "WA8USED", 0)
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segmk.addtag(loc, "WEMUX.CE", bels != ['LUT6', 'LUT6', 'LUT6', 'LUT6'])
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def bitfilter(frame_idx, bit_idx):
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# Hack to remove aliased PIP bits
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# We should either mix up routing more or exclude previous DB entries
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assert os.getenv("XRAY_DATABASE") == "artix7"
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return (frame_idx, bit_idx) not in [(0, 27), (1, 25), (1, 26), (1, 29)]
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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