mirror of https://github.com/openXC7/prjxray.git
53 lines
1.4 KiB
Tcl
53 lines
1.4 KiB
Tcl
create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports c]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports d]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports q]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets c_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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source ../../utils/utils.tcl
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foreach it {
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{b11 INT_L_X12Y100/GCLK_L_B11}
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{b10 INT_L_X12Y100/GCLK_L_B10}
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{b9 INT_L_X12Y100/GCLK_L_B9}
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{b8 INT_L_X12Y100/GCLK_L_B8}
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{b7 INT_L_X12Y100/GCLK_L_B7}
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{b6 INT_L_X12Y100/GCLK_L_B6}
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{b5 INT_R_X13Y100/GCLK_B5}
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{b4 INT_R_X13Y100/GCLK_B4}
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{b3 INT_R_X13Y100/GCLK_B3}
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{b2 INT_R_X13Y100/GCLK_B2}
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{b1 INT_R_X13Y100/GCLK_B1}
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{b0 INT_R_X13Y100/GCLK_B0}
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} {
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set net [get_nets c_IBUF_BUFG]
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set_property FIXED_ROUTE {} $net
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route_design -unroute -net $net
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set id [lindex $it 0]
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set gclk [lindex $it 1]
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route_via $net "$gclk"
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write_checkpoint -force design_$id.dcp
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write_bitstream -force design_$id.bit
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}
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