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prjxray/fuzzers/018-clb-ram
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Jake Mercer c05b4b0406 MAKE - Format Trailing Whitespace 
Add `make format-trailing-ws`.  This recipe finds all _files_ (not
links) known to Git and uses `sed` to remove trailing whitespace.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 		2019-10-26 10:04:52 +01:00
..
minitest MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00
Makefile 018-clb-ram: Increase specimen count 2019-05-24 08:05:41 +02:00
README.md docs: Fix top level headers and other small clean. 2019-04-03 19:26:28 -07:00
generate.py fuzzers: name with tile type 2019-01-07 23:08:45 +01:00
generate.sh fuzzers: name with tile type 2019-01-07 23:08:45 +01:00
generate.tcl fuzzers: name with tile type 2019-01-07 23:08:45 +01:00
top.py 01x-clb/top.py: Added CLBN increment from env var 2019-01-17 15:31:50 +01:00

README.md

clb-ram Fuzzer

Primitive RAM SMALL SRL
LUT6
SRL16E X X
SRLC32E X
RAM32X1S X X
RAM64X1S X
RAM32M X X
RAM32X1D X X
RAM64M X
RAM64X1D X
RAM128X1D X
RAM256X1S X
RAM128X1S X

NLUT.RAM

Set to make a RAM* family primitive, otherwise is a SRL or LUT function generator.

NLUT.SMALL

Seems to be set on smaller primitives.

NLUT.SRL

Whether to make a shift register LUT (SRL). Set when using SRL16E or SRLC32E

WA7USED

Set to 1 to propagate CLB's CX input to WA7

WA8USED

Set to 1 to propagate CLB's BX input to WA8

WEMUX.CE

WEMUX.CE CLB RAM write enable
0 CLB WE input
1 CLB CE input