Alessandro Comodi 2d62f223d6 grid: update test data and make format ...

Signed-off-by: Alessandro Comodi <[email protected]>

2020-03-24 20:27:26 +01:00

..

__init__.py

…

bitfilter.py

make format.

2019-01-17 18:45:00 -08:00

bitsmaker.py

tilegrid iob: factor out generic code

2018-12-18 13:20:57 -08:00

bitstream.py

MAKE - Format Trailing Whitespace

2019-10-26 10:04:52 +01:00

connections.py

Add ROI annotations and update some missing tilegrid changes.

2018-10-05 18:26:24 -07:00

db.py

Move all part-specific files to dedicated directory

2020-01-24 10:13:33 +01:00

fasm_assembler.py

Add pin functions to tilegrid.

2019-10-14 16:38:02 -07:00

fasm_disassembler.py

IOB_SING solution via segbit aliases.

2019-03-01 17:02:18 -08:00

grid_types.py

grid: update test data and make format

2020-03-24 20:27:26 +01:00

grid.py

grid: add prohibited sites to GridType

2020-03-24 18:41:13 +01:00

lib.py

074-dump-all: stabilized naming of sites

2019-02-13 17:58:41 +01:00

lms_solver.py

Move all part-specific files to dedicated directory

2020-01-24 10:13:33 +01:00

lut_maker.py

Add fuzzer for BRAM/FIFO enable bits.

2019-02-04 15:39:20 -08:00

math_models.py

Fix some comments.

2019-05-09 14:20:03 -07:00

node_lookup.py

make format.

2019-01-17 21:48:34 -08:00

roi.py

Run make format.

2018-10-22 12:32:42 -07:00

segmaker.py

Do not assert if XRAY_PART env variable is not present

2020-01-24 10:13:33 +01:00

segment_map.py

Run make format.

2018-10-19 16:19:22 -07:00

site_type.py

prjxray: Add INOUT to direction enum.

2019-03-14 15:20:01 -07:00

state_gen.py

Move StateGen to own file, and ran make format.

2019-02-18 10:02:48 -08:00

tile_segbits_alias.py

Enable ppips even on aliased segbit files.

2019-10-14 16:42:52 -07:00

tile_segbits.py

IOB_SING solution via segbit aliases.

2019-03-01 17:02:18 -08:00

tile.py

Correct units factor on resistances.

2019-05-21 07:13:23 -07:00

timing.py

Fix formatting

2019-05-23 12:04:50 +02:00

util.py

Do not assert if XRAY_PART env variable is not present

2020-01-24 10:13:33 +01:00

verilog.py

FUZZER - DSP - Add Ports & ROI Module

2019-11-02 11:43:12 +00:00

xjson.py

Remove broken special case logic from xjson.

2020-02-18 15:48:02 -08:00