mirror of https://github.com/openXC7/prjxray.git
661 lines
24 KiB
Python
661 lines
24 KiB
Python
#!/usr/bin/env python3
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import os, sys, json, re
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'''
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Historically we grouped data into "segments"
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These were a region of the bitstream that encoded one or more tiles
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However, this didn't scale with certain tiles like BRAM
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Some sites had multiple bitstream areas and also occupied multiple tiles
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Decoding was then shifted to instead describe how each title is encoded
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A post processing step verifies that two tiles don't reference the same bitstream area
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'''
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from generate import load_tiles
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from prjxray import util
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def nolr(tile_type):
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'''
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Remove _L or _R suffix tile_type suffix, if present
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Ex: BRAM_INT_INTERFACE_L => BRAM_INT_INTERFACE
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Ex: VBRK => VBRK
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'''
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postfix = tile_type[-2:]
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if postfix in ('_L', '_R'):
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return tile_type[:-2]
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else:
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return tile_type
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def load_baseaddrs(deltas_fns):
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site_baseaddr = dict()
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for arg in deltas_fns:
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with open(arg) as f:
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line = f.read().strip()
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# clb/design_SLICE_X10Y100.delta
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# site = arg[7:-6]
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site = re.match(r".*/design_(.*).delta", arg).group(1)
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# +bit_00400026_100_02
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_, frame_str, _, _ = line.split('_')
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frame = int(frame_str, 16)
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site_baseaddr[site] = frame & ~0x7f
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return site_baseaddr
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def make_tile_baseaddrs(tiles, site_baseaddr, verbose=False):
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# Look up a base address by tile name
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tile_baseaddrs = dict()
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verbose and print('')
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verbose and print('%u tiles' % len(tiles))
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verbose and print("%u baseaddrs" % len(site_baseaddr))
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added = 0
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for tile in tiles:
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for site_name in tile["sites"].keys():
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if site_name not in site_baseaddr:
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continue
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framebaseaddr = site_baseaddr[site_name]
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bt = util.addr2btype(framebaseaddr)
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tile_baseaddr = tile_baseaddrs.setdefault(tile["name"], {})
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if bt in tile_baseaddr:
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# actually lets just fail these, better to remove at tcl level to speed up processing
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assert 0, 'duplicate base address'
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assert tile_baseaddr[bt] == [framebaseaddr, 0]
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else:
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tile_baseaddr[bt] = [framebaseaddr, 0]
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verbose and print(
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"baseaddr: %s.%s @ %s.0x%08x" %
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(tile["name"], site_name, bt, framebaseaddr))
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added += 1
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assert added, "Failed to add any base addresses"
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assert added == len(site_baseaddr)
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return tile_baseaddrs
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def make_tiles_by_grid(tiles):
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# lookup tile names by (X, Y)
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tiles_by_grid = dict()
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for tile in tiles:
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tiles_by_grid[(tile["grid_x"], tile["grid_y"])] = tile["name"]
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return tiles_by_grid
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def add_segment(
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database, segments, name, tiles, segtype, verbose, baseaddr=None):
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assert name not in segments
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segment = segments.setdefault(name, {})
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segment["tiles"] = tiles
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segment["type"] = segtype
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if baseaddr:
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verbose and print('make_segment: %s baseaddr %s' % (
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name,
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baseaddr,
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))
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segment["baseaddr"] = baseaddr
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for tile_name in tiles:
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database[tile_name]["segment"] = name
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def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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'''
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Create segments data structure
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Indicates how tiles are related to bitstream locations
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Also modify database to annotate which segment the tiles belong to
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segments key examples:
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SEG_CLBLM_R_X13Y72
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SEG_BRAM3_L_X6Y85
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'''
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segments = dict()
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verbose and print('')
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for tile_name, tile_data in database.items():
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tile_type = tile_data["type"]
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grid_x = tile_data["grid_x"]
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grid_y = tile_data["grid_y"]
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def add_segment(name, tiles, segtype, baseaddr=None):
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assert name not in segments
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segment = segments.setdefault(name, {})
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segment["tiles"] = tiles
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segment["type"] = segtype
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if baseaddr:
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verbose and print(
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'make_segment: %s baseaddr %s' % (
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name,
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baseaddr,
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))
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segment["baseaddr"] = baseaddr
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for tile_name in tiles:
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database[tile_name]["segment"] = name
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def process_clb():
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if tile_type in ["CLBLL_L", "CLBLM_L"]:
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int_tile_name = tiles_by_grid[(grid_x + 1, grid_y)]
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else:
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int_tile_name = tiles_by_grid[(grid_x - 1, grid_y)]
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add_segment(
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name="SEG_" + tile_name,
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tiles=[tile_name, int_tile_name],
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segtype=tile_type.lower(),
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baseaddr=tile_baseaddrs.get(tile_name, None))
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def process_hclk():
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add_segment(
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name="SEG_" + tile_name,
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tiles=[tile_name],
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segtype=tile_type.lower())
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def process_iob():
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tiles = [tile_name]
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# FIXME mcmaster: removing INT for now
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# Geometry doesn't line up with CLB, unclear if they are included
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if tile_type.startswith('LIOB'):
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# Two INT_L's
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# tiles.append(tiles_by_grid[(grid_x + 4, grid_y)])
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# tiles.append(tiles_by_grid[(grid_x + 4, grid_y - 1)])
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# One IO interface tile
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tiles.append(tiles_by_grid[(grid_x + 1, grid_y)])
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else:
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# Two INT_R's
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# tiles.append(tiles_by_grid[(grid_x - 4, grid_y)])
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# tiles.append(tiles_by_grid[(grid_x - 4, grid_y - 1)])
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# One IO interface tile
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tiles.append(tiles_by_grid[(grid_x - 1, grid_y)])
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add_segment(
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name="SEG_" + tile_name,
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tiles=tiles,
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segtype=tile_type.lower(),
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baseaddr=tile_baseaddrs.get(tile_name, None))
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def process_iob_sing():
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# FIXME mcmaster: removing INT for now
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# Geometry doesn't line up with CLB, unclear if they are included
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tiles = [tile_name]
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if tile_type.startswith('LIOB'):
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tiles.append(tiles_by_grid[(grid_x + 1, grid_y)])
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# tiles.append(tiles_by_grid[(grid_x + 4, grid_y)])
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else:
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tiles.append(tiles_by_grid[(grid_x - 1, grid_y)])
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# tiles.append(tiles_by_grid[(grid_x - 4, grid_y)])
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add_segment(
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name="SEG_" + tile_name,
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tiles=tiles,
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segtype=tile_type.lower(),
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baseaddr=tile_baseaddrs.get(tile_name, None))
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def process_bram_dsp():
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for k in range(5):
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if tile_type in ["BRAM_L", "DSP_L"]:
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interface_tile_name = tiles_by_grid[(
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grid_x + 1, grid_y - k)]
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int_tile_name = tiles_by_grid[(grid_x + 2, grid_y - k)]
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elif tile_type in ["BRAM_R", "DSP_R"]:
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interface_tile_name = tiles_by_grid[(
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grid_x - 1, grid_y - k)]
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int_tile_name = tiles_by_grid[(grid_x - 2, grid_y - k)]
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else:
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assert 0
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'''
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BRAM/DSP itself is at the base y address
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There is one huge switchbox on the right for the 5 tiles
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These fan into 5 BRAM_INT_INTERFACE tiles each which feed into their own CENTER_INTER (just like a CLB has)
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'''
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if k == 0:
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tiles = [tile_name, interface_tile_name, int_tile_name]
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baseaddr = tile_baseaddrs.get(tile_name, None)
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else:
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tiles = [interface_tile_name, int_tile_name]
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baseaddr = None
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add_segment(
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# BRAM_L_X6Y70 => SEG_BRAM4_L_X6Y70
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name="SEG_" + tile_name.replace("_", "%d_" % k, 1),
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tiles=tiles,
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# BRAM_L => bram4_l
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segtype=tile_type.lower().replace("_", "%d_" % k, 1),
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baseaddr=baseaddr)
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def process_default():
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verbose and nolr(tile_type) not in (
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'VBRK', 'INT', 'NULL') and print(
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'make_segment: drop %s' % (tile_type, ))
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pass
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"""
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FIXME: review IOB
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"RIOB33": process_iob,
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"LIOB33": process_iob,
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"RIOB33_SING": process_iob_sing,
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"LIOB33_SING": process_iob_sing,
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"""
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{
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"CLBLL": process_clb,
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"CLBLM": process_clb,
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"HCLK": process_hclk,
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"BRAM": process_bram_dsp,
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"DSP": process_bram_dsp,
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}.get(nolr(tile_type), process_default)()
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return segments
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def get_inttile(database, segment):
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'''Return interconnect tile for given segment'''
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return (
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tile for tile in segment["tiles"]
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if database[tile]["type"] in ["INT_L", "INT_R"])
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def get_iobtile(database, segment):
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'''Return IOB tile for given segment'''
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return (
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tile for tile in segment["tiles"]
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if database[tile]["type"] in ["LIOB33_SING", "LIOB33"])
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def get_bramtile(database, segment):
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inttiles = [
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tile for tile in segment["tiles"]
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if database[tile]["type"] in ["BRAM_L", "BRAM_R"]
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]
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assert len(inttiles) == 1
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return inttiles[0]
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def create_segment_for_int_lr(
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database, segments, tile, tiles_by_grid, verbose):
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""" Creates INT_[LR] segment for interconnect's without direct connectivity. """
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# Some INT_[LR] tiles have no adjacent connectivity, create a segment.
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grid_x = database[tile]["grid_x"]
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grid_y = database[tile]["grid_y"]
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if database[tile]["type"] == "INT_L":
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grid_x -= 1
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adjacent_tile = tiles_by_grid[(grid_x, grid_y)]
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elif database[tile]["type"] == "INT_R":
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grid_x += 1
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adjacent_tile = tiles_by_grid[(grid_x, grid_y)]
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else:
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assert False, database[tile]["type"]
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if (database[adjacent_tile]['type'].startswith('INT_INTERFACE_') or
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database[adjacent_tile]['type'].startswith('PCIE_INT_INTERFACE_')
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or
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database[adjacent_tile]['type'].startswith('GTP_INT_INTERFACE')):
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# This INT_[LR] tile has no adjacent connectivity,
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# create a segment.
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add_segment(
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database=database,
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segments=segments,
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name='SEG_' + tile,
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tiles=[tile],
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segtype=database[tile]["type"],
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verbose=verbose,
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)
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else:
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assert False, database[adjacent_tile]['type']
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def seg_base_addr_lr_INT(database, segments, tiles_by_grid, verbose=False):
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'''Populate segment base addresses: L/R along INT column'''
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'''
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Create BRAM base addresses based on nearby CLBs
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ie if we have a BRAM_L, compute as nearby CLB_R base address + offset
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'''
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verbose and print('')
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for segment_name in sorted(segments.keys()):
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segment = segments[segment_name]
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baseaddrs = segment.get("baseaddr", None)
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if not baseaddrs:
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continue
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for block_type, (framebase, wordbase) in sorted(baseaddrs.items()):
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verbose and print(
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'lr_INT: %s: %s.0x%08X:%u' %
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(segment_name, block_type, framebase, wordbase))
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if block_type != 'CLB_IO_CLK':
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verbose and print(' Skip non CLB')
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continue
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for inttile in get_inttile(database, segment):
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grid_x = database[inttile]["grid_x"]
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grid_y = database[inttile]["grid_y"]
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if database[inttile]["type"] == "INT_L":
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grid_x += 1
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framebase = framebase + 0x80
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elif database[inttile]["type"] == "INT_R":
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grid_x -= 1
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framebase = framebase - 0x80
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else:
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assert 0
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# ROI at edge?
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if (grid_x, grid_y) not in tiles_by_grid:
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verbose and print(' Skip edge')
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continue
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tile = tiles_by_grid[(grid_x, grid_y)]
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if database[inttile]["type"] == "INT_L":
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assert database[tile]["type"] == "INT_R"
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elif database[inttile]["type"] == "INT_R":
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assert database[tile]["type"] == "INT_L"
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else:
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assert 0
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if "segment" not in database[tile]:
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continue
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seg = database[tile]["segment"]
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seg_baseaddrs = segments[seg].setdefault("baseaddr", {})
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# At least one duplicate when we re-compute the entry for the base address
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# should give the same address
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if block_type in seg_baseaddrs:
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assert seg_baseaddrs[block_type] == [
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framebase, wordbase
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], (seg_baseaddrs[block_type], [framebase, wordbase])
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verbose and print(' Existing OK')
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else:
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seg_baseaddrs[block_type] = [framebase, wordbase]
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verbose and print(' Add new')
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def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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'''Populate segment base addresses: Up along INT/HCLK columns'''
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verbose and print('')
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# Copy the initial list containing only base addresses
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# and soon to have derived addresses
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src_segment_names = list()
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for segment_name in segments.keys():
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if "baseaddr" in segments[segment_name]:
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src_segment_names.append(segment_name)
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verbose and print('up_INT: %u base addresses' % len(src_segment_names))
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for src_segment_name in sorted(src_segment_names):
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src_segment = segments[src_segment_name]
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for block_type, (framebase,
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wordbase) in sorted(src_segment["baseaddr"].items()):
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verbose and print(
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'up_INT: %s: %s.0x%08X:%u' %
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(src_segment_name, block_type, framebase, wordbase))
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def process_CLB_IO_CLK(wordbase):
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'''
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Lookup interconnect tile associated with this segment
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Use it to locate in the grid, and find other segments related by tile offset
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'''
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for inttile in list(get_inttile(database, src_segment)) + list(
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get_iobtile(database, src_segment)):
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verbose and print(
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' up_INT CLK_IO_CLK: %s => inttile %s' %
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(src_segment_name, inttile),
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file=sys.stderr)
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grid_x = database[inttile]["grid_x"]
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grid_y = database[inttile]["grid_y"]
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for i in range(50):
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grid_y -= 1
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loc = (grid_x, grid_y)
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if loc not in tiles_by_grid:
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continue
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dst_tile = database[tiles_by_grid[loc]]
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if 'segment' not in dst_tile:
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continue
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#assert 'segment' in dst_tile, ((grid_x, grid_y), dst_tile, tiles_by_grid[(grid_x, grid_y)])
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if wordbase == 50:
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wordbase += 1
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else:
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wordbase += 2
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#verbose and print(' dst_tile', dst_tile)
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dst_segment_name = dst_tile["segment"]
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#verbose and print('up_INT: %s => %s' % (src_segment_name, dst_segment_name))
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segments[dst_segment_name].setdefault(
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"baseaddr",
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{})[block_type] = [framebase, wordbase]
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def process_BLOCK_RAM(wordbase):
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'''
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Lookup BRAM0 tile associated with this segment
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Use it to locate in the grid, and find other BRAM0 related by tile offset
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From minitest:
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build/roi_bramd_bit01.diff (lowest BRAM coordinate)
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> bit_00c00000_000_00
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build/roi_bramds_bit01.diff
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> bit_00c00000_000_00
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> bit_00c00000_010_00
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> bit_00c00000_020_00
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> bit_00c00000_030_00
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> bit_00c00000_040_00
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> bit_00c00000_051_00
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> bit_00c00000_061_00
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> bit_00c00000_071_00
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> bit_00c00000_081_00
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> bit_00c00000_091_00
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'''
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src_tile_name = get_bramtile(database, src_segment)
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verbose and print(
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' up_INT BLOCK_RAM: %s => %s' %
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(src_segment_name, src_tile_name))
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grid_x = database[src_tile_name]["grid_x"]
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grid_y = database[src_tile_name]["grid_y"]
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for i in range(9):
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grid_y -= 5
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wordbase += 10
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# Skip HCLK
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if i == 4:
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grid_y -= 1
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wordbase += 1
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# FIXME: PCIE block cuts out some BRAM
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# this messes up algorithm as is and may cause this to fail
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dst_tile_name = tiles_by_grid[(grid_x, grid_y)]
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dst_tile = database[dst_tile_name]
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assert nolr(dst_tile['type']) == 'BRAM', dst_tile
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dst_segment_name = dst_tile["segment"]
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verbose and print(
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' up_INT BLOCK_RAM: %s => %s' %
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(dst_segment_name, dst_tile_name))
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assert 'BRAM0' in dst_segment_name
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segments[dst_segment_name].setdefault(
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"baseaddr", {})[block_type] = [framebase, wordbase]
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{
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'CLB_IO_CLK': process_CLB_IO_CLK,
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'BLOCK_RAM': process_BLOCK_RAM,
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}[block_type](
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wordbase)
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def add_tile_bits(tile_db, baseaddr, offset, frames, words, height=None):
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'''
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Record data structure geometry for the given tile baseaddr
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For most tiles there is only one baseaddr, but some like BRAM have multiple
|
|
Notes on multiple block types:
|
|
https://github.com/SymbiFlow/prjxray/issues/145
|
|
'''
|
|
|
|
bits = tile_db['bits']
|
|
block_type = util.addr2btype(baseaddr)
|
|
|
|
assert 0 <= offset <= 100, offset
|
|
assert 1 <= words <= 101
|
|
assert offset + words <= 101, (
|
|
tile_db, offset + words, offset, words, block_type)
|
|
|
|
assert block_type not in bits
|
|
block = bits.setdefault(block_type, {})
|
|
|
|
# FDRI address
|
|
block["baseaddr"] = '0x%08X' % baseaddr
|
|
# Number of frames this entry is sretched across
|
|
# that is the following FDRI addresses are used: range(baseaddr, baseaddr + frames)
|
|
block["frames"] = frames
|
|
|
|
# Index of first word used within each frame
|
|
block["offset"] = offset
|
|
|
|
# related to words...
|
|
# deprecated field? Don't worry about for now
|
|
# DSP has some differences between height and words
|
|
block["words"] = words
|
|
if height is None:
|
|
height = words
|
|
block["height"] = height
|
|
|
|
|
|
def db_add_bits(database, segments):
|
|
'''Transfer segment data into tiles'''
|
|
for segment_name in segments.keys():
|
|
if 'baseaddr' not in segments[segment_name]:
|
|
continue
|
|
|
|
for block_type, (baseaddr,
|
|
offset) in segments[segment_name]["baseaddr"].items():
|
|
for tile_name in segments[segment_name]["tiles"]:
|
|
tile_type = database[tile_name]["type"]
|
|
"""
|
|
FIXME: review IOB
|
|
# IOB
|
|
# design_IOB_X0Y100.delta:+bit_00020027_000_29
|
|
# design_IOB_X0Y104.delta:+bit_00020027_008_29
|
|
# design_IOB_X0Y112.delta:+bit_00020027_024_29
|
|
# design_IOB_X0Y120.delta:+bit_00020027_040_29
|
|
# design_IOB_X0Y128.delta:+bit_00020027_057_29
|
|
# design_IOB_X0Y136.delta:+bit_00020027_073_29
|
|
# design_IOB_X0Y144.delta:+bit_00020027_089_29
|
|
# $XRAY_BLOCKWIDTH design_IOB_X0Y100.bit |grep 00020000
|
|
# 0x00020000: 0x2A (42)
|
|
("RIOI3", "CLB_IO_CLK"): (42, 2, 4),
|
|
("LIOI3", "CLB_IO_CLK"): (42, 2, 4),
|
|
("RIOI3_SING", "CLB_IO_CLK"): (42, 2, 4),
|
|
("LIOI3_SING", "CLB_IO_CLK"): (42, 2, 4),
|
|
("RIOI3_TBYTESRC", "CLB_IO_CLK"): (42, 2, 4),
|
|
("LIOI3_TBYTESRC", "CLB_IO_CLK"): (42, 2, 4),
|
|
("RIOI3_TBYTETERM", "CLB_IO_CLK"): (42, 2, 4),
|
|
("LIOI3_TBYTETERM", "CLB_IO_CLK"): (42, 2, 4),
|
|
("LIOB33", "CLB_IO_CLK"): (42, 2, 4),
|
|
("RIOB33", "CLB_IO_CLK"): (42, 2, 4),
|
|
("LIOB33", "CLB_IO_CLK"): (42, 2, 4),
|
|
("RIOB33_SING", "CLB_IO_CLK"): (42, 2, 4),
|
|
("LIOB33_SING", "CLB_IO_CLK"): (42, 2, 4),
|
|
"""
|
|
entry = {
|
|
# (tile_type, block_type): (frames, words, height)
|
|
("CLBLL", "CLB_IO_CLK"): (36, 2, 2),
|
|
("CLBLM", "CLB_IO_CLK"): (36, 2, 2),
|
|
("HCLK", "CLB_IO_CLK"): (26, 1, 1),
|
|
("INT", "CLB_IO_CLK"): (28, 2, 2),
|
|
("BRAM", "CLB_IO_CLK"): (28, 10, None),
|
|
("BRAM", "BLOCK_RAM"): (128, 10, None),
|
|
("DSP", "CLB_IO_CLK"): (28, 2, 10),
|
|
("INT_INTERFACE", "CLB_IO_CLK"): (28, 2, None),
|
|
("BRAM_INT_INTERFACE", "CLB_IO_CLK"): (28, 2, None),
|
|
}.get((nolr(tile_type), block_type), None)
|
|
if entry is None:
|
|
# Other types are rare, not expected to have these
|
|
if block_type == "CLB_IO_CLK":
|
|
raise ValueError("Unknown tile type %s" % tile_type)
|
|
continue
|
|
|
|
frames, words, height = entry
|
|
if frames:
|
|
# if we have a width, we should have a height
|
|
assert frames and words
|
|
add_tile_bits(
|
|
database[tile_name], baseaddr, offset, frames, words,
|
|
height)
|
|
|
|
|
|
def db_add_segments(database, segments):
|
|
# TODO: Migrate to new tilegrid format via library. This data is added for
|
|
# compability with unconverted tools. Update tools then remove this data from
|
|
# tilegrid.json.
|
|
# looks like only htmlgen is using this?
|
|
for tiledata in database.values():
|
|
if "segment" in tiledata:
|
|
segment = tiledata["segment"]
|
|
tiledata["segment_type"] = segments[segment]["type"]
|
|
|
|
|
|
def run(json_in_fn, json_out_fn, tiles_fn, deltas_fns, verbose=False):
|
|
# Load input files
|
|
tiles = load_tiles(tiles_fn)
|
|
site_baseaddr = load_baseaddrs(deltas_fns)
|
|
|
|
database = json.load(open(json_in_fn, "r"))
|
|
|
|
tile_baseaddrs = make_tile_baseaddrs(tiles, site_baseaddr, verbose=verbose)
|
|
tiles_by_grid = make_tiles_by_grid(tiles)
|
|
|
|
segments = make_segments(
|
|
database, tiles_by_grid, tile_baseaddrs, verbose=verbose)
|
|
|
|
# Reference adjacent CLBs to locate adjacent tiles by known offsets
|
|
seg_base_addr_lr_INT(database, segments, tiles_by_grid, verbose=verbose)
|
|
seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=verbose)
|
|
|
|
db_add_bits(database, segments)
|
|
db_add_segments(database, segments)
|
|
|
|
# Save
|
|
json.dump(
|
|
database,
|
|
open(json_out_fn, "w"),
|
|
sort_keys=True,
|
|
indent=4,
|
|
separators=(",", ": "))
|
|
|
|
|
|
def main():
|
|
import argparse
|
|
import glob
|
|
|
|
parser = argparse.ArgumentParser(
|
|
description="Generate tilegrid.json from bitstream deltas")
|
|
|
|
parser.add_argument("--verbose", action="store_true", help="")
|
|
parser.add_argument(
|
|
"--json-in",
|
|
default="tiles_basic.json",
|
|
help="Input .json without addresses")
|
|
parser.add_argument(
|
|
"--json-out", default="tilegrid.json", help="Output JSON")
|
|
parser.add_argument(
|
|
'--tiles', default='tiles.txt', help='Input tiles.txt tcl output')
|
|
parser.add_argument(
|
|
"deltas", nargs="*", help=".bit diffs to create base addresses from")
|
|
args = parser.parse_args()
|
|
|
|
deltas = args.deltas
|
|
if not args.deltas:
|
|
deltas = glob.glob("*.delta")
|
|
|
|
run(args.json_in, args.json_out, args.tiles, deltas, verbose=args.verbose)
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|