mirror of https://github.com/openXC7/prjxray.git
61 lines
1.8 KiB
Python
61 lines
1.8 KiB
Python
#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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import re
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REBUF_GCLK = re.compile('^CLK_BUFG_REBUF_R_CK_GCLK([0-9]+)_BOT$')
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def main():
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segmk = Segmaker("design.bits")
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print("Loading tags from design.txt.")
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gclks_in_use = {}
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with open("design.txt", "r") as f:
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for line in f:
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if 'CLK_BUFG_REBUF' not in line:
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continue
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parts = line.replace('{', '').replace('}','').strip().replace('\t', ' ').split(' ')
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dst = parts[0]
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pip = parts[3]
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tile_from_pip, pip = pip.split('/')
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if 'CLK_BUFG_REBUF' not in tile_from_pip:
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continue
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tile_type, pip = pip.split('.')
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assert tile_type == 'CLK_BUFG_REBUF'
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wire_a, wire_b = pip.split('<<->>')
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tile_from_wire, dst = dst.split('/')
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assert dst == wire_a
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m = REBUF_GCLK.match(dst)
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assert m, dst
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gclk = int(m.group(1))
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if tile_from_pip not in gclks_in_use:
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gclks_in_use[tile_from_pip] = set()
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gclks_in_use[tile_from_pip].add(gclk)
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if tile_from_wire == tile_from_pip:
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segmk.add_tile_tag(tile_from_pip, '{}.{}'.format(wire_a, wire_b), wire_a == dst)
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segmk.add_tile_tag(tile_from_pip, '{}.{}'.format(wire_b, wire_a), wire_a != dst)
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else:
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segmk.add_tile_tag(tile_from_pip, '{}.{}'.format(wire_a, wire_b), wire_a != dst)
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segmk.add_tile_tag(tile_from_pip, '{}.{}'.format(wire_b, wire_a), wire_a == dst)
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for tile, gclks in gclks_in_use.items():
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for gclk in range(2):
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segmk.add_tile_tag(tile, 'GCLK{}_ENABLED'.format(gclk), gclk in gclks)
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segmk.compile()
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segmk.write(allow_empty=True)
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if __name__ == '__main__':
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main()
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