mirror of https://github.com/openXC7/prjxray.git
42 lines
1.6 KiB
ReStructuredText
42 lines
1.6 KiB
ReStructuredText
Bitstream format
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================
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.. todo::
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Expand on rough notes
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* Specific byte pattern at beginning of file to allow hardware to determine
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width of bus providing configuration data.
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* Rest of file is 32-bit big-endian words
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* All data before 32-bit synchronization word (0xAA995566) is ignored by
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configuration state machine
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* Packetized format used to perform register reads/writes
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* Three packet header types
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* Type 0 packets exist only when performing zero-fill between rows
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* Type 1 used for writes up to 4096 words
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* Type 2 expands word count field to 27 bits by omitting register address
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* Type 2 must always be proceeded by Type 1 which sets register address
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* NOP packets are used for inserting required delays
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* Most registers only accept 1 word of data
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* Allowed register operations depends on interface used to send packets
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* Writing LOUT via JTAG is treated as a bad command
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* Single-frame FDRI writes via JTAG fail
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* CRC
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* Calculated automatically from writes: register address and data written
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* Expected value is written to CRC register
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* If there is a mismatch, error is flagged in status register
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* Writes to CRC register can be safely removed from a bitstream
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* Alternatively, replace with write to command register to reset calculated
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CRC value
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* Xilinx BIT header
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* Additional information about how bitstream was generated
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* Unofficially documented at
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http://www.fpga-faq.com/FAQ_Pages/0026_Tell_me_about_bit_files.htm
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* Really does require NULL-terminated Pascal strings
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* Having this header is the distinction between .bin and .bit in Vivado
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* Is ignored entirely by devices
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