mirror of https://github.com/openXC7/prjxray.git
80 lines
1.7 KiB
Python
Executable File
80 lines
1.7 KiB
Python
Executable File
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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'''
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This script generates a verilog ROM module that contains data to be transmitted
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and received. The data is random.
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'''
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import random
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def main():
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template = """
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`default_nettype none
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// ============================================================================
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module rom
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(
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input wire CLK,
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input wire RST,
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input wire RD,
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output wire [{rom_width_minus_one}:0] O
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);
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// ============================================================================
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reg [{rom_width_minus_one}:0] rom[0:{rom_size_minus_one}];
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initial begin
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{rom_data}
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end
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reg [{rom_width_minus_one}:0] dat;
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reg [{rom_size_bits_minus_one}:0] adr;
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always @(posedge CLK)
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if (RST) adr <= 0;
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else if (RD) adr <= adr + 1;
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always @(posedge CLK)
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if (RD) dat <= rom[adr];
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assign O = dat;
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// ============================================================================
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endmodule
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"""
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rom_size_bits = 5
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rom_size = 2**rom_size_bits
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rom_width = 8
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rom_data = [random.randint(0, 2**rom_width - 1) for i in range(rom_size)]
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rom_data = "\n".join(
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[
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" rom[%4d] <= %d'd%d;" % (i, rom_width, d)
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for i, d in enumerate(rom_data)
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])
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print(
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template.format(
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rom_size_bits_minus_one=rom_size_bits - 1,
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rom_size_minus_one=rom_size - 1,
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rom_width_minus_one=rom_width - 1,
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rom_data=rom_data))
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if __name__ == "__main__":
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main()
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