mirror of https://github.com/openXC7/prjxray.git
105 lines
3.3 KiB
ReStructuredText
105 lines
3.3 KiB
ReStructuredText
==========
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mask files
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==========
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The *mask files* are generated for every FPGA :term:`tile <tile>` type. They store
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the information, which bits in the bitstream can configure the given
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:term:`tile <tile>` type.
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Naming convention
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-----------------
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The naming scheme for the mask files is the following::
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mask_<tile>.db
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Note that auxiliary ``mask_<tile>.origin_info.db`` files
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provide additional information about the :term:`fuzzer <fuzzer>`,
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which produced the :term:`database <database>` file. This file is optional.
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Every :term:`tile <tile>` is configured at least by one of three configurational
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buses mentioned in the :doc:`Configuration Section <../../architecture/configuration>`.
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The default bus is called ``CLB_IO_CLK``. If the :term:`tile <tile>` can also be
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configured by another bus it has additional ``mask_<tile>.<bus_name>.db``
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related to that bus.
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In example:
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- ``mask_dsp_r.db``
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- ``mask_bram_l.db`` (configured with default ``CLB_IO_CLK`` bus)
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- ``mask_bram_l.block_ram.db`` (configured with ``BLOCK_RAM`` bus)
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File format
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-----------
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The file consist of the records that describes configuration bits for
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the particular :term:`tile <tile>` type. Each entry inside the file is of the form::
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bit <frame_address_offset>_<bit_position>
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This means that the :term:`tile <tile>` can be configured by bit located in the
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:term:`frame <frame>` at the address ``<base_frame_addr> + <frame_address_offset>``,
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at position ``<tile_offset> + <bit_position>``. Information about ``<base_frame_address>``
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and ``<tile_offset>`` can be taken from part specific ``tilegrid.json`` file.
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Example
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-------
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Below there is a part of artix7 ``mask_clbll_l.db`` file describing FPGA *CLBLL*
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:term:`tile <tile>`::
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<...>
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bit 00_61
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bit 00_62
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bit_00_63
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bit 01_00
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bit 01_01
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bit 01_02
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<...>
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The line ``bit 01_02`` means that the *CLBL_LL* :term:`tile <tile>` can be
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configured by the bit located in the :term:`frame <frame>` at the address
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``<base_frame_address> + 0x01``, at position ``<tile_offset> + 0x2``.
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The ``tilegrid.json`` is a file specific to a given chip package.
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For *xc7a35tcpg236-1* we can find exemplary *CLBLL_L* entry::
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"CLBLL_L_X2Y0": {
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"bits": {
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"CLB_IO_CLK": {
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"baseaddr": "0x00400100",
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"frames": 36,
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"offset": 0,
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"words": 2
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}
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},
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"clock_region": "X0Y0",
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"grid_x": 10,
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"grid_y": 155,
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"pin_functions": {},
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"sites": {
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"SLICE_X0Y0": "SLICEL",
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"SLICE_X1Y0": "SLICEL"
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},
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"type": "CLBLL_L"
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},
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The ``<base_frame_addr>`` can be found as a argument of the *"baseaddr"* key
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and for *CLBLL_L_X2Y0* :term:`tile <tile>` it is equal to ``0x00400100``. The ``<tile_offset>``
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on the other hand is an argument of the *"offset"* key. Here it is equal to 0.
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Finally, we are able to compute the bit location associated with the
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``bit 01_02`` entry.
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The configuration bit for this record can be found in the following
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:term:`frame <frame>` address::
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0x00400100 + 0x01 = 0x00400101
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Located at the bit position::
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0x0 + 0x2 = 0x2
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More about the configuration process and the meaning of the :term:`frame <frame>`
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can be found in the :doc:`Configuration Section <../../architecture/configuration>`.
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