History

Karol Gugala 5fcfc4d61b fuzzers: 017: rename PRECYINIT_{0\|1} -> PRECYINIT_{C0\|C1} Signed-off-by: Karol Gugala <kgugala@antmicro.com>		2019-01-02 21:30:56 +01:00
..
Makefile	clb.mk: fix fuzzer include, seg .rdb => .db	2018-11-07 20:04:54 -08:00
README.md	Added tags for headers, subheaders and structured README files a bit	2018-02-14 12:24:18 +01:00
bits.dbf	fuzzers: 017: rename PRECYINIT_{0\|1} -> PRECYINIT_{C0\|C1}	2019-01-02 21:30:56 +01:00
generate.py	fuzzers: 017: rename PRECYINIT_{0\|1} -> PRECYINIT_{C0\|C1}	2019-01-02 21:30:56 +01:00
generate.sh	dbfixup: patch local files instead of central db	2018-11-07 14:28:31 -08:00
generate.tcl	tcl: reformat existing code	2018-12-05 16:52:56 -08:00
top.py	017-clbprecyinit: base SLICE X/Y on ROI X/Y	2018-11-07 20:04:54 -08:00

README.md

CLBPRECYINIT Fuzzer

Purpose

Document PRECYINIT mux

Algorithm

Outcome

CLB.SLICE_X0.PRECYINIT.0 <0 candidates>
CLB.SLICE_X0.PRECYINIT.1 00_12
CLB.SLICE_X0.PRECYINIT.AX 30_14
CLB.SLICE_X0.PRECYINIT.CIN 30_13
CLB.SLICE_X1.PRECYINIT.0 <0 candidates>
CLB.SLICE_X1.PRECYINIT.1 01_11
CLB.SLICE_X1.PRECYINIT.AX 31_13
CLB.SLICE_X1.PRECYINIT.CIN 31_12