mirror of https://github.com/openXC7/prjxray.git
222 lines
9.2 KiB
Tcl
222 lines
9.2 KiB
Tcl
# General notes:
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# Observed nets with 1 to 2 source cell pins
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# 2 example
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# [get_pins -filter {DIRECTION == OUT} -of_objects $net]
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# roi/dout_shr[0]_i_1/O: BEL, visible
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# roi/dout_shr_reg[0]: no BEL, not visible, named after the net
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# I don't understand what the relationship between these two is
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# Maybe register retiming?
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# Observed nets with 0 to 1 source bel pins
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# 0 example: <const0>
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# Recommendation: assume there is at most one source BEL
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# Take that as the source BEL if it exists, otherwise don't do any source analysis
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# get_timing_paths vs get_net_delays
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# get_timing_paths is built on top of get_net_delays?
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# has some different info, but is fixed on the slow max corner
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# *possibly* reports slightly better info within a site, but would need to verify that
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# Things safe to assume:
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# -Each net has at least one delay?
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# -Cell exists for every delay path
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# -Each net has at least one destination BEL pin
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# Things not safe to assume
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# -Each net has at least one source BEL pin (ex: <const0>)
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proc list_format {l delim} {
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set ret ""
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set needspace 0
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foreach x $l {
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if $needspace {
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set ret "$ret$delim$x"
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} else {
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set ret "$x"
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}
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set needspace 1
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}
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return $ret
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}
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proc line_net_external {fp net src_site src_site_type src_site_pin src_bel src_bel_pin dst_site dst_site_type dst_site_pin dst_bel dst_bel_pin ico fast_max fast_min slow_max slow_min pips_out wires_out} {
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puts $fp "NET,$net,$src_site,$src_site_type,$src_site_pin,$src_bel,$src_bel_pin,$dst_site,$dst_site_type,$dst_site_pin,$dst_bel,$dst_bel_pin,$ico,$fast_max,$fast_min,$slow_max,$slow_min,$pips_out,$wires_out"
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}
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proc line_net_internal {fp net site site_type src_bel src_bel_pin dst_bel dst_bel_pin ico fast_max fast_min slow_max slow_min} {
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set src_site $site
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set src_site_type $site_type
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set src_site_pin ""
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set dst_site $site
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set dst_site_type $site_type
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set dst_site_pin ""
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set pips_out ""
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set wires_out ""
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puts $fp "NET,$net,$src_site,$src_site_type,$src_site_pin,$src_bel,$src_bel_pin,$dst_site,$dst_site_type,$dst_site_pin,$dst_bel,$dst_bel_pin,$ico,$fast_max,$fast_min,$slow_max,$slow_min,$pips_out,$wires_out"
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}
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proc write_info4 {} {
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set outdir "."
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set fp [open "$outdir/timing4.txt" w]
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# bel as site/bel, so don't bother with site
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puts $fp "linetype,net,src_site,src_site_type,src_site_pin,src_bel,src_bel_pin,dst_site,dst_site_type,dst_site_pin,dst_bel,dst_bel_pin,ico,fast_max,fast_min,slow_max,slow_min,pips,wires"
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set TIME_start [clock clicks -milliseconds]
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set delays_net 0
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set nets_no_src_cell 0
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set nets_no_src_bel 0
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set lines_no_int 0
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set lines_some_int 0
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set neti 0
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set nets [get_nets -hierarchical]
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#set nets [get_nets clk]
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#set nets [get_nets roi/counter[0]_i_2_n_0]
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set nnets [llength $nets]
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foreach net $nets {
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incr neti
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puts "Net $neti / $nnets: $net"
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# there are some special places like on IOB where you may not have a cell source pin
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# this is due to special treatment where BEL vs SITE are blurred
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# The semantics of get_pins -leaf is kind of odd
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# When no passthrough LUTs exist, it has no effect
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# When passthrough LUT present:
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# -w/o -leaf: some pins + passthrough LUT pins
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# -w/ -leaf: different pins + passthrough LUT pins
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# With OUT filter this seems to be sufficient
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set src_cell_pins [get_pins -leaf -filter {DIRECTION == OUT} -of_objects $net]
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if {$src_cell_pins eq ""} {
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incr nets_no_src_cell
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# ex: IOB internal bel net
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puts " SKIP: no source cell"
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continue
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}
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# 0 to 2 of these
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# Seems when 2 of them they basically have the same bel + cell
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# Make a best effort and move forward
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set src_cell_pin [lindex $src_cell_pins 0]
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set src_cell [get_cells -of_objects $src_cell_pin]
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# Only applicable if in a site
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set src_bel [get_bels -of_objects $src_cell]
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if {$src_bel eq ""} {
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# just throw out cases where source site doesn't exist
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# these are very special, don't really have timing info anyway
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# rework these later if they become problematic
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incr nets_no_src_bel
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puts " SKIP: no source bel"
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continue
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}
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set src_bel_pin [get_bel_pins -of_objects $src_cell_pin]
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set src_site [get_sites -of_objects $src_bel]
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set src_site_type [get_property SITE_TYPE $src_site]
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# optional
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set src_site_pin [get_site_pins -of_objects $src_cell_pin]
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# Report delays with and without interconnect only
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foreach ico "0 1" {
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if $ico {
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set delays [get_net_delays -interconnect_only -of_objects $net]
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} else {
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set delays [get_net_delays -of_objects $net]
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}
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set delays_net [expr "$delays_net + [llength $delays]"]
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puts $fp "GROUP,$ico,[llength $delays]"
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foreach delay $delays {
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#set delaystr [get_property NAME $delay]
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set fast_max [get_property "FAST_MAX" $delay]
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set fast_min [get_property "FAST_MIN" $delay]
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set slow_max [get_property "SLOW_MAX" $delay]
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set slow_min [get_property "SLOW_MIN" $delay]
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# Does this always exist?
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set dst_cell_pin_str [get_property TO_PIN $delay]
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set dst_cell_pin [get_pins $dst_cell_pin_str]
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set dst_cell [get_cells -of_objects $dst_cell_pin]
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set dst_bel [get_bels -of_objects $dst_cell]
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# WARNING: when there is a passthrough LUT, this can be multiple values
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# (one for the real dest pin, and one for the passthrough lut input)
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set dst_bel_pin [get_bel_pins -of_objects $dst_cell_pin]
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set dst_site [get_sites -of_objects $dst_bel]
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set dst_site_type [get_property SITE_TYPE $dst_site]
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# optional
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set dst_site_pin [get_site_pins -of_objects $dst_cell_pin]
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# No fabric on this net?
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# don't try querying sites and such
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if {[get_nodes -of_objects $net] eq ""} {
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if {$src_site ne $dst_site} {
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puts "ERROR: site mismatch"
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return
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}
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if {$src_site_type ne $dst_site_type} {
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puts "ERROR: site mismatch"
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return
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}
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# Already have everything we could query
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# Just output
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incr lines_no_int
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line_net_internal $fp $net $src_site $src_site_type $src_bel $src_bel_pin $dst_bel $dst_bel_pin $ico $fast_max $fast_min $slow_max $slow_min
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# At least some fabric exists
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# Does dest BEL exist but not source BEL?
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} elseif {$src_bel eq ""} {
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puts "ERROR: should have been filtered"
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return
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# Ideally query from and to cell pins
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} else {
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# Nested list delimination precedence: ",|:"
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# Pips in between
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# Walk net, looking for interesting elements in between
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# -from <args> - (Optional) Defines the starting points of the pips to get
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# from wire or site_pin
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set pips [get_pips -of_objects $net -from $src_site_pin -to $dst_site_pin]
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# Write pips w/ speed index
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foreach pip $pips {
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set speed_index [get_property SPEED_INDEX $pip]
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lappend pips_out "$pip:$speed_index"
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}
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set pips_out [list_format "$pips_out" "|"]
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set nodes [get_nodes -of_objects $net -from $src_site_pin -to $dst_site_pin]
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if {$nodes eq ""} {
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puts "ERROR: no nodes"
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return
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}
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set wires [get_wires -of_objects $nodes]
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# Write wires
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foreach wire $wires {
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set speed_index [get_property SPEED_INDEX $wire]
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lappend wires_out "$wire:$speed_index"
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}
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set wires_out [list_format "$wires_out" "|"]
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incr lines_some_int
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line_net_external $fp $net $src_site $src_site_type $src_site_pin $src_bel $src_bel_pin $dst_site $dst_site_type $dst_site_pin $dst_bel $dst_bel_pin $ico $fast_max $fast_min $slow_max $slow_min $pips_out $wires_out
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}
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}
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}
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}
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close $fp
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set TIME_taken [expr [clock clicks -milliseconds] - $TIME_start]
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puts "Took ms: $TIME_taken"
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puts "Checked $delays_net delays"
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puts "Nets: $nnets"
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puts " Skipped (no source cell): $nets_no_src_cell"
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puts " Skipped (no source bel): $nets_no_src_bel"
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puts "Lines"
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puts " No interconnect: $lines_no_int"
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puts " Has interconnect: $lines_some_int"
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}
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# for debugging
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# source ../project.tcl
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# write_info4
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