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prjxray
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prjxray/minitests/ps7/xtra
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Maciej Kurc cb26746128 Added dumping of dummy inout ports, added generation of techmap that ties unconnected ports to 0. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 		2020-01-28 09:19:40 +01:00
..
Makefile Added dumping of dummy inout ports, added generation of techmap that ties unconnected ports to 0. 2020-01-28 09:19:40 +01:00
README.md Added dumping of dummy inout ports, added generation of techmap that ties unconnected ports to 0. 2020-01-28 09:19:40 +01:00
dump_ps7.tcl Added dumping of dummy inout ports, added generation of techmap that ties unconnected ports to 0. 2020-01-28 09:19:40 +01:00
make_cell.py Added dumping of dummy inout ports, added generation of techmap that ties unconnected ports to 0. 2020-01-28 09:19:40 +01:00

README.md

PS7 verilog cell definition extractor

Extracts all pins of the PS7 bel from Vivado, groups them into buses, removes those that are not connected (TEST*, DEBUG*) and creates the VPR counterpart for it. It also generates model XML, pb_type XML and techmap which handles unconnected ports correctly.