mirror of https://github.com/openXC7/prjxray.git
46 lines
1.5 KiB
Tcl
46 lines
1.5 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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puts "FUZ([pwd]): Creating project"
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create_project -force -part $::env(XRAY_PART) design design
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puts "FUZ([pwd]): Reading verilog"
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read_verilog $::env(FUZDIR)/top.v
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read_verilog $::env(FUZDIR)/picorv32.v
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puts "FUZ([pwd]): Synth design"
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports din]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports dout]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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set_param tcl.collectionResultDisplayLimit 0
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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randplace_pblock 100 roi
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puts "FUZ([pwd]): Placing design"
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place_design
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puts "FUZ([pwd]): Routing design"
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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