mirror of https://github.com/openXC7/prjxray.git
259 lines
8.0 KiB
Tcl
259 lines
8.0 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc load_todo {{dir "dst"}} {
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set fp [open "../../todo_all.txt" r]
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# Create map of pip source to remaining destinations for that pip
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set todo_map [dict create]
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for {gets $fp line} {$line != ""} {gets $fp line} {
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set parts [split $line .]
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if {$dir == "dsts"} {
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dict lappend todo_map [lindex $parts 2] [list [lindex $parts 0] [lindex $parts 1]]
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} elseif {$dir == "srcs"} {
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dict lappend todo_map [lindex $parts 1] [list [lindex $parts 0] [lindex $parts 2]]
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} else {
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error "Incorrect argument. Available options: src, dst"
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}
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}
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close $fp
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return $todo_map
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}
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proc shuffle_list {list} {
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set l [llength $list]
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for {set i 0} {$i<=$l} {incr i} {
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set x [lindex $list [set p [expr {int(rand()*$l)}]]]
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set list [lreplace $list $p $p]
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set list [linsert $list [expr {int(rand()*$l)}] $x]
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}
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return $list
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}
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# Get the dictionary of nets with one corresponding source wire
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# of a PIP from the todo list
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proc get_nets_with_todo_pip_wires {direction net_regexp wire_regexp used_destinations {verbose false}} {
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set todo_map [load_todo $direction]
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puts $todo_map
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set nets [get_nets]
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set todo_nets [dict create]
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foreach net $nets {
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if {![regexp $net_regexp $net]} {
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continue
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}
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# Check to see if this net is one we are interested in*
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set wires [get_wires -of_objects $net -filter {TILE_NAME =~ "*HCLK_IOI*" } -quiet]
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set wire_found 0
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foreach wire $wires {
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if [regexp $wire_regexp $wire] {
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set wire_found 1
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break
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}
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}
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if {$wire_found == 0} {
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if {$verbose} {
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puts "$net not going to a HCLK port, skipping."
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}
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continue
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}
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set tile [lindex [split $wire /] 0]
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set wire [lindex [split $wire /] 1]
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set tile_type [get_property TILE_TYPE [get_tiles $tile]]
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if { ![dict exists $todo_map $wire] } {
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continue
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}
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set candidates [dict get $todo_map $wire]
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# This net is interesting, see if it is already going somewhere we
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# want.
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set found_target 0
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foreach other_wire $wires {
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if { $found_target == 1 } {
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break
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}
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set other_wire [lindex [split $other_wire /] 1]
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if { $wire == $other_wire } {
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continue
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}
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foreach candidate $candidates {
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set candidate_tile_type [lindex $candidate 0]
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if {$candidate_tile_type != $tile_type} {
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continue
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}
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set candidate_wire [lindex $candidate 1]
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if { $other_wire == $candidate } {
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set found_target 1
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if {$verbose} {
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puts "Interesting net $net already going from $wire to $other_wire."
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}
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set_property IS_ROUTE_FIXED 1 $net
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dict set used_destinations "$tile/$candidate_wire" 1
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break
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}
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}
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}
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if { $found_target == 1 } {
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# Net already has an interesting feature - don't reroute.
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continue
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}
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dict set todo_nets $net [list $tile $wire]
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if {$verbose} {
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puts "Interesting net $net (including $wire) is being rerouted."
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}
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}
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return $todo_nets
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}
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proc route_todo {} {
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set used_destinations [dict create]
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set todo_map [load_todo "srcs"]
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set idelayctrl_nets [get_nets_with_todo_pip_wires "srcs" "IDELAYCTRL" "HCLK_IOI_IDELAYCTRL_REFCLK" $used_destinations]
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puts "Idelayctrl nets: $idelayctrl_nets"
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dict for {net tile_wire} $idelayctrl_nets {
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set tile [lindex $tile_wire 0]
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set wire [lindex $tile_wire 1]
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set srcs [dict get $todo_map $wire]
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set tile_type [get_property TILE_TYPE [get_tiles $tile]]
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set todos {}
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set old_origin_wire [get_wires -of_objects $net -filter {TILE_NAME =~ "*HCLK_IOI*" && NAME =~ "*HCLK_IOI_LEAF_GCLK_*"}]
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if {$old_origin_wire == {}} {
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continue
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}
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puts "Rerouting net $net at $tile / $wire (type $tile_type)"
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puts "Previous target wire: $old_origin_wire"
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set old_origin_node [get_nodes -of_objects $old_origin_wire]
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if [regexp "HCLK_IOI_LEAF_GCLK_\(\(TOP\)|\(BOT\)\).*" $old_origin_wire match group] {
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set old_target_side $group
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}
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foreach src $srcs {
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set src_tile_type [lindex $src 0]
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if {$src_tile_type != $tile_type} {
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continue
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}
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set src_wire [lindex $src 1]
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set is_gclk_net 0
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if [regexp "HCLK_IOI_LEAF_GCLK_\(\(TOP\)|\(BOT\)\).*" $src_wire match group] {
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set is_gclk_net 1
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}
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if {$is_gclk_net == 0} {
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continue
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}
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lappend todos $src_wire
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}
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set todos_length [llength $todos]
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if {$todos_length == 0} {
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continue
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}
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puts "All todos for $tile_type / $wire"
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foreach src_wire $todos {
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puts " - $src_wire"
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}
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set todos [shuffle_list $todos]
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set target_node [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]]
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puts "Target node: $target_node"
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route_design -unroute -nets $net
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# Find an output in the todo list that can drive.
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foreach src_wire $todos {
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if { [dict exists $used_destinations "$tile/$src_wire"] } {
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puts "Not routing to $tile / $src_wire, in use."
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continue
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}
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set origin_wire [get_wires "$tile/$src_wire"]
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set origin_node [get_nodes -of_objects $origin_wire]
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if {[llength $origin_node] == 0} {
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error "Failed to find node for $tile/$src_wire."
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}
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set old_net [get_nets -of_objects $origin_node -quiet]
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if {$old_net != {}} {
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puts "Unrouting the old net: $old_net"
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route_design -unroute -nets $old_net
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}
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# Route the net through the desired node
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puts "Attempting to route to $src_wire for net $net."
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route_via $net [list $origin_node]
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puts "Target node: $target_node"
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puts "Origin wire: $origin_wire, Old origin wire: $old_origin_wire"
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puts "Origin node: $origin_node, Old origin node: $old_origin_node"
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dict set used_destinations "$origin_wire" 1
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break
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}
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-38}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-13}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-123}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-1575}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-1684}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-1712}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-78}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-81}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design
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route_design
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route_todo
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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