mirror of https://github.com/openXC7/prjxray.git
108 lines
2.7 KiB
Tcl
108 lines
2.7 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc make_io_pin_sites {} {
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# get all possible IOB pins
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foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
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set site [get_sites -of_objects $pad]
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if {[llength $site] == 0} {
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continue
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}
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if [string match IOB33* [get_property SITE_TYPE $site]] {
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dict append io_pin_sites $site $pad
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}
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}
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return $io_pin_sites
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}
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proc load_pin_lines {} {
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# IOB_X0Y103 clk input
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# IOB_X0Y129 do[0] output
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set fp [open "params.csv" r]
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gets $fp line
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set pin_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend pin_lines [split $line ","]
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}
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close $fp
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return $pin_lines
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}
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proc loc_pins {} {
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set pin_lines [load_pin_lines]
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set io_pin_sites [make_io_pin_sites]
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puts "Looping"
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for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} {
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set line [lindex $pin_lines $idx]
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puts "$line"
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set site_str [lindex $line 1]
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set pin_str [lindex $line 2]
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set iostandard [lindex $line 3]
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set drive [lindex $line 4]
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set slew [lindex $line 5]
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set pulltype [lindex $line 6]
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# Have: site
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# Want: pin for site
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set site [get_sites $site_str]
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set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}]
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# set port [get_ports -of_objects $site]
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set port [get_ports $pin_str]
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set tile [get_tiles -of_objects $site]
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set pin [dict get $io_pin_sites $site]
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set props {}
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#lappend props PACKAGE_PIN $pin
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lappend props IOSTANDARD $iostandard
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lappend props PULLTYPE $pulltype
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if {$drive != "None"} {
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lappend props DRIVE $drive
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}
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if {$slew != "None"} {
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lappend props SLEW $slew
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}
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puts $props
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set_property -dict "$props" $port
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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loc_pins
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-144}]
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write_checkpoint -force design_pre_place.dcp
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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