mirror of https://github.com/openXC7/prjxray.git
97 lines
2.7 KiB
Tcl
97 lines
2.7 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
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[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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########################################
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# Unmodified design with random LUTs
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proc write_txtdata {filename} {
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puts "Writing $filename."
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set fp [open $filename w]
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foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] {
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set bel [get_property BEL $cell]
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set loc [get_property LOC $cell]
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set init [get_property INIT $cell]
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puts $fp "$loc $bel $init"
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}
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close $fp
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}
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write_bitstream -force design_0.bit
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write_txtdata design_0.txt
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########################################
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# XOR LUT INITs
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set pattern_list {
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0x1234567812345678
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0xFFFFFFFF00000000
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0xFFFF0000FFFF0000
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0xFF00FF00FF00FF00
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0xF0F0F0F0F0F0F0F0
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0xCCCCCCCCCCCCCCCC
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0xAAAAAAAAAAAAAAAA
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}
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set pattern_index 0
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foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] {
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set v [get_property init $cell]
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set v [scan [string range $v 4 100] %x]
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set v [expr $v ^ [lindex $pattern_list $pattern_index]]
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set v [format %x $v]
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set_property init 64'h$v $cell
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set pattern_index [expr ($pattern_index + 1) % 7]
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}
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write_bitstream -force design_1.bit
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write_txtdata design_1.txt
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########################################
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# Set LUT INITs
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set pattern_index 1
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foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] {
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set_property init 64'h[lindex $pattern_list $pattern_index] $cell
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set pattern_index [expr ($pattern_index + 1) % 7]
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}
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write_bitstream -force design_2.bit
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write_txtdata design_2.txt
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