mirror of https://github.com/openXC7/prjxray.git
70 lines
1.8 KiB
Tcl
70 lines
1.8 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc create_design {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(SRC_DIR)/top.v
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synth_design -top top -flatten_hierarchy none
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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}
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proc place_and_route_design {} {
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place_design
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route_design
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write_checkpoint -force design.dcp
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}
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proc dump_model_timings {timing_fp models} {
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set properties [list "DELAY" "FAST_MAX" "FAST_MIN" "SLOW_MAX" "SLOW_MIN"]
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foreach model $models {
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set timing_line {}
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lappend timing_line "$model"
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foreach property $properties {
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set value [get_property $property [get_speed_models -patterns $model]]
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lappend timing_line "$property:$value"
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}
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puts $timing_fp $timing_line
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}
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}
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proc dump {} {
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set slicel_fp [open "slicel.txt" w]
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set slicem_fp [open "slicem.txt" w]
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set slicel_speed_models [get_speed_models -patterns *_sl_*]
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set slicem_speed_models [get_speed_models -patterns *_sm_*]
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dump_model_timings $slicel_fp $slicel_speed_models
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dump_model_timings $slicem_fp $slicem_speed_models
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close $slicel_fp
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close $slicem_fp
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}
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proc run {} {
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create_design
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place_and_route_design
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dump
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write_bitstream -force design.bit
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}
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run
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