mirror of https://github.com/openXC7/prjxray.git
50 lines
1.7 KiB
Tcl
50 lines
1.7 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
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[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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proc write_txtdata {filename} {
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puts "Writing $filename."
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set fp [open $filename w]
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foreach tile [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] {
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puts "Dumping pips from tile $tile"
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foreach pip [get_pips -of_objects $tile] {
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if {[get_nets -quiet -of_objects $pip] == {}} {puts $fp "$pip 0"} {puts $fp "$pip 1"}
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}
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}
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close $fp
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}
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write_bitstream -force design.bit
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write_txtdata design.txt
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