mirror of https://github.com/openXC7/prjxray.git
119 lines
2.9 KiB
Verilog
119 lines
2.9 KiB
Verilog
module top(input clk, stb, di, output do);
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localparam integer DIN_N = 256;
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localparam integer DOUT_N = 256;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [255:0] din, output [255:0] dout);
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clb_NCY0_MX # (.LOC("SLICE_X20Y100"), .BEL("A6LUT"), .N(0))
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am (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 8]));
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clb_NCY0_O5 # (.LOC("SLICE_X20Y101"), .BEL("A6LUT"), .N(0))
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a5 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[8 +: 8]));
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clb_NCY0_MX # (.LOC("SLICE_X20Y102"), .BEL("B6LUT"), .N(1))
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bm (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[16 +: 8]));
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clb_NCY0_O5 # (.LOC("SLICE_X20Y103"), .BEL("B6LUT"), .N(1))
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b5 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[24 +: 8]));
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clb_NCY0_MX # (.LOC("SLICE_X20Y104"), .BEL("C6LUT"), .N(2))
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cm (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[32 +: 8]));
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clb_NCY0_O5 # (.LOC("SLICE_X20Y105"), .BEL("C6LUT"), .N(2))
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c5 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[40 +: 8]));
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clb_NCY0_MX # (.LOC("SLICE_X20Y106"), .BEL("D6LUT"), .N(3))
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dm (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[48 +: 8]));
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clb_NCY0_O5 # (.LOC("SLICE_X20Y107"), .BEL("D6LUT"), .N(3))
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d5 (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[56 +: 8]));
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endmodule
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module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X16Y129_FIXME";
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parameter BEL="A6LUT_FIXME";
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parameter N=-1;
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wire [3:0] o;
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assign dout[0] = o[1];
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wire o6, o5;
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reg [3:0] s;
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always @(*) begin
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s = din[7:4];
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s[N] = o6;
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end
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o5),
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.O6(o6));
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
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endmodule
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module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X16Y129_FIXME";
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parameter BEL="A6LUT_FIXME";
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parameter N=-1;
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wire [3:0] o;
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assign dout[0] = o[1];
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wire o6, o5;
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reg [3:0] s;
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reg [3:0] di;
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always @(*) begin
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s = din[7:4];
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s[N] = o6;
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di = {din[3:0]};
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di[N] = o5;
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end
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o5),
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.O6(o6));
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
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endmodule
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