mirror of https://github.com/openXC7/prjxray.git
122 lines
3.4 KiB
Python
122 lines
3.4 KiB
Python
#!/usr/bin/env python3
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'''
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FDCE Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear
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FDPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset
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FDRE Primitive: D Flip-Flop with Clock Enable and Synchronous Reset
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FDSE Primitive: D Flip-Flop with Clock Enable and Synchronous Set
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LDCE Primitive: Transparent Data Latch with Asynchronous Clear and Gate Enable
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LDPE Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable
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'''
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from prims import *
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from prjxray.segmaker import Segmaker
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segmk = Segmaker("design.bits")
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def ones(l):
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#return l + [x + '_1' for x in l]
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#return sorted(l + [x + '_1' for x in l])
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ret = []
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for x in l:
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ret.append(x)
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ret.append(x + '_1')
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return ret
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def loadtop():
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'''
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i,prim,loc,bel
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0,FDPE,SLICE_X12Y100,C5FF
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1,FDPE,SLICE_X15Y100,A5FF
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2,FDPE_1,SLICE_X16Y100,B5FF
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3,LDCE_1,SLICE_X17Y100,BFF
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'''
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f = open('top.txt', 'r')
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f.readline()
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ret = {}
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for l in f:
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i, prim, loc, bel, init = l.split(",")
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i = int(i)
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init = int(init)
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ret[loc] = (i, prim, loc, bel, init)
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return ret
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top = loadtop()
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def vs2i(s):
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return {"1'b0": 0, "1'b1": 1}[s]
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print("Loading tags from design.txt")
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with open("design.txt", "r") as f:
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for line in f:
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'''
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puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
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CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X13Y137/AFF REG_INIT 1 FDRE
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CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X12Y137/D5FF FF_INIT 0
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'''
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line = line.split()
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tile_type = line[0]
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tile_name = line[1]
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grid_x = line[2]
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grid_y = line[3]
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# Other code uses BEL name
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# SLICE_X12Y137/D5FF
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site_ff_name = line[4]
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site, ff_name = site_ff_name.split('/')
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ff_type = line[5]
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used = int(line[6])
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cel_prim = None
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cel_name = None
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if used:
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cel_name = line[7]
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# ex: FDCE
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cel_prim = line[8]
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# 1'b1
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# cinv = int(line[9][-1])
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cinv = int(line[9])
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init = vs2i(line[10])
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#init = int(line[10])
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# A B C D
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which = ff_name[0]
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# LUT6 vs LUT5 FF
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is5 = '5' in ff_name
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if used:
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segmk.add_site_tag(site, "%s.ZINI" % ff_name, 1 ^ init)
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# CLKINV turns out to be more complicated than origianlly thought
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if isff(cel_prim):
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segmk.add_site_tag(site, "CLKINV", cinv)
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segmk.add_site_tag(site, "NOCLKINV", 1 ^ cinv)
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else:
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segmk.add_site_tag(site, "CLKINV", 1 ^ cinv)
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segmk.add_site_tag(site, "NOCLKINV", cinv)
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# Synchronous vs asynchronous FF
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# Unlike most bits, shared between all CLB FFs
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segmk.add_site_tag(site, "FFSYNC", cel_prim in ('FDSE', 'FDRE'))
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# Latch bit
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# Only applies to LUT6 (non-5) FF's
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if not is5:
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segmk.add_site_tag(site, "LATCH", isl(cel_prim))
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'''
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On name:
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The primitives you listed have a control input to set the FF value to zero (clear/reset),
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the other three primitives have a control input that sets the FF value to one.
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Z => inversion
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'''
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segmk.add_site_tag(
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site, "%s.ZRST" % ff_name,
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cel_prim in ('FDRE', 'FDCE', 'LDCE'))
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segmk.compile()
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segmk.write()
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