mirror of https://github.com/openXC7/prjxray.git
126 lines
4.0 KiB
Python
126 lines
4.0 KiB
Python
#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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def isenv_tags(segmk, ps, site):
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# all of these bits are inverted
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ks = [
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('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
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('IS_CLKBWRCLK_INVERTED', 'ZINV_CLKBWRCLK'),
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('IS_ENARDEN_INVERTED', 'ZINV_ENARDEN'),
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('IS_ENBWREN_INVERTED', 'ZINV_ENBWREN'),
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('IS_RSTRAMARSTRAM_INVERTED', 'ZINV_RSTRAMARSTRAM'),
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('IS_RSTRAMB_INVERTED', 'ZINV_RSTRAMB'),
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('IS_RSTREGARSTREG_INVERTED', 'ZINV_RSTREGARSTREG'),
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('IS_RSTREGB_INVERTED', 'ZINV_RSTREGB'),
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]
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for param, tagname in ks:
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segmk.add_site_tag(site, tagname, 1 ^ verilog.parsei(ps[param]))
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def bus_tags(segmk, ps, site):
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'''
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parameter DOA_REG = 1'b0;
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parameter DOB_REG = 1'b0;
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parameter SRVAL_A = 18'b0;
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parameter SRVAL_B = 18'b0;
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parameter INIT_A = 18'b0;
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parameter INIT_B = 18'b0;
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'''
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for param, tagname in [('SRVAL_A', 'ZSRVAL_A'), ('SRVAL_B', 'ZSRVAL_B'),
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('INIT_A', 'ZINIT_A'), ('INIT_B', 'ZINIT_B')]:
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bitstr = verilog.parse_bitstr(ps[param])
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ab = param[-1]
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# Are all bits present?
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hasparity = ps['READ_WIDTH_' + ab] == 18
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for i in range(18):
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# Magic bit positions from experimentation
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# we could just only solve when parity, but this check documents the fine points a bit better
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if hasparity or i not in (1, 9):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
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def rw_width_tags(segmk, ps, site):
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'''
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Y0.READ_WIDTH_A
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width 001_03 001_04 001_05
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1 0 0 0
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2 1 0 0
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4 0 1 0
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9 1 1 0
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18 0 0 1
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'''
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'''
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for param, vals in {
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"READ_WIDTH_A": [1, 2, 4, 9, 18],
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"READ_WIDTH_B": [1, 2, 4, 9, 18],
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"WRITE_WIDTH_A": [1, 2, 4, 9, 18],
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"WRITE_WIDTH_B": [1, 2, 4, 9, 18],
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}.items():
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set_val = int(ps[param])
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for val in vals:
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has = set_val == val
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segmk.add_site_tag(site, '%s_B0' % (param), has)
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'''
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for param in ["READ_WIDTH_A", "READ_WIDTH_B", "WRITE_WIDTH_A",
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"WRITE_WIDTH_B"]:
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set_val = int(ps[param])
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# Multiple bits (not one hot)
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# segmk.add_site_tag(site, '%s_B0' % (param), set_val in (2, 9))
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# segmk.add_site_tag(site, '%s_B1' % (param), set_val in (4, 9))
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# segmk.add_site_tag(site, '%s_B2' % (param), set_val in (18, ))
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# 1 is special in that its all 0's
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# diff only against that
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segmk.add_site_tag(site, '%s_%u' % (param, 1), set_val != 1)
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for widthn in [2, 4, 9, 18]:
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if set_val == 1:
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segmk.add_site_tag(site, '%s_%u' % (param, widthn), False)
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elif set_val == widthn:
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segmk.add_site_tag(site, '%s_%u' % (param, widthn), True)
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def write_mode_tags(segmk, ps, site):
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for param in ["WRITE_MODE_A", "WRITE_MODE_B"]:
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set_val = verilog.unquote(ps[param])
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# WRITE_FIRST: no bits set
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segmk.add_site_tag(
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site, '%s_READ_FIRST' % (param), set_val == "READ_FIRST")
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segmk.add_site_tag(
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site, '%s_NO_CHANGE' % (param), set_val == "NO_CHANGE")
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def run():
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segmk = Segmaker("design.bits")
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#segmk.set_def_bt('BLOCK_RAM')
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print("Loading tags")
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f = open('params.jl', 'r')
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f.readline()
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for l in f:
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j = json.loads(l)
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ps = j['params']
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assert j['module'] == 'my_RAMB18E1'
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site = verilog.unquote(ps['LOC'])
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#print('site', site)
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isenv_tags(segmk, ps, site)
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bus_tags(segmk, ps, site)
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rw_width_tags(segmk, ps, site)
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write_mode_tags(segmk, ps, site)
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def bitfilter(frame, bit):
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# rw_width_tags() aliasing interconnect on large widths
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return frame not in (20, 21)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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run()
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