mirror of https://github.com/openXC7/prjxray.git
72 lines
2.8 KiB
Plaintext
72 lines
2.8 KiB
Plaintext
Timing analysis fuzzer
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This runs some random designs through Vivado and extracts timing information in order to derive timing models
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While Vivado has more involved RC (spice?) models incorporating fanout and other things,
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for now we are shooting for simple, conservative models with a min and max timing delay
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Background
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Vivado seems to associate each delay model with a "speed index"
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In particular, we are currently looking at pips and wires, each of which have a speed index associated with them
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For every timeing path, we record the total delay from one site to another, excluding site delays
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(timing analyzer provides an option to make this easy)
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We then walk along the path and record all wires and pips in between
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These are converted to their associated speed indexes
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This gives an equation that a series of speed indexes was given a certain delay value
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These equations are then fed into scipy.optimize.linprog to give estimates for the delay models
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However, there are some complications. For example:
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Given a system of equations like:
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t0 = 5
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t0 + t1 = 10
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t0 + t1 + t2 = 12
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The solver puts all the delays in t0
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To get around this, we subtract equations from each other
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Some additional info here: https://github.com/SymbiFlow/prjxray/wiki/Timing
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Quick start
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./speed.sh
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python timfuz_delay.py --cols-max 9 timfuz_dat/s1_timing2.txt
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Which will report something like
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Delay on 36 / 162
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Now add some more data in:
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python timfuz_delay.py --cols-max 9 timfuz_dat/speed_json.json timfuz_dat/s*_timing2.txt
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Which should get a few more delay elements, say:
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Delay on 57 / 185
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From scratch
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Roughly something like this
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Edit generate.tcl
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Uncomment speed_models2
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Run "make N=1"
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python speed_json.py specimen_001/speed_model.txt speed_json.json
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Edit generate.tcl
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Comment speed_models2
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Run "make N=4" to generate some more timing data
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Now run as in the quick start
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python timfuz_delay.py --cols-max 9 speed_json.json specimen_*/timing2.txt
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TODO:
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Verify elements are being imported correctly throughout the whole chain
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Can any wires or similar be aggregated?
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Ex: if a node consisents of two wire delay models and that pair is never seen elsewhere
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Look at virtual switchboxes. Can these be removed?
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Look at suspicous elements like WIRE_RC_ZERO
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