mirror of https://github.com/openXC7/prjxray.git
168 lines
4.6 KiB
Python
168 lines
4.6 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import json
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import os
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import random
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from collections import namedtuple
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.lut_maker import LutMaker
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from prjxray.db import Database
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INT = "INT"
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BIN = "BIN"
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BOOL = "BOOL"
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STR = "STR"
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def gen_sites(site):
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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already_used = list()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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if gridinfo.tile_type not in [
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"GTX_CHANNEL_0",
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"GTX_CHANNEL_1",
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"GTX_CHANNEL_2",
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"GTX_CHANNEL_3",
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"GTX_CHANNEL_0_MID_LEFT",
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"GTX_CHANNEL_1_MID_LEFT",
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"GTX_CHANNEL_2_MID_LEFT",
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"GTX_CHANNEL_3_MID_LEFT",
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"GTX_CHANNEL_0_MID_RIGHT",
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"GTX_CHANNEL_1_MID_RIGHT",
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"GTX_CHANNEL_2_MID_RIGHT",
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"GTX_CHANNEL_3_MID_RIGHT",
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] or gridinfo.tile_type in already_used:
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continue
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else:
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tile_type = gridinfo.tile_type
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already_used.append(tile_type)
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for site_name, site_type in gridinfo.sites.items():
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if site_type != site:
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continue
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if "RIGHT" in tile_type and "X0" in site_name:
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continue
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if "LEFT" in tile_type and "X1" in site_name:
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continue
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yield tile_name, tile_type, site_name, site_type
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def main():
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print(
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'''
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module top(
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input wire in,
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output wire out
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);
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assign out = in;
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''')
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luts = LutMaker()
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primitives_list = list()
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for tile_name, tile_type, site_name, site_type in gen_sites(
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"GTXE2_CHANNEL"):
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params_list = list()
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params_dict = dict()
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params_dict["tile_type"] = tile_type
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params = dict()
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params['site'] = site_name
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verilog_attr = ""
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verilog_attr = "#("
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fuz_dir = os.getenv("FUZDIR", None)
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assert fuz_dir
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with open(os.path.join(fuz_dir, "attrs.json"), "r") as attrs_file:
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attrs = json.load(attrs_file)
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in_use = bool(random.randint(0, 9))
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params["IN_USE"] = in_use
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if in_use:
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for param, param_info in attrs.items():
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param_type = param_info["type"]
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param_values = param_info["values"]
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param_digits = param_info["digits"]
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if param_type == INT:
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value = random.choice(param_values)
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value_str = value
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elif param_type == BIN:
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value = random.randint(0, param_values[0])
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value_str = "{digits}'b{value:0{digits}b}".format(
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value=value, digits=param_digits)
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elif param_type in [BOOL, STR]:
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value = random.choice(param_values)
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value_str = verilog.quote(value)
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params[param] = value
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verilog_attr += """
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.{}({}),""".format(param, value_str)
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verilog_ports = ""
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for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
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"RXUSRCLK", "RXUSRCLK2", "DRPCLK"]:
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is_inverted = random.randint(0, 1)
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params[param] = is_inverted
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verilog_attr += """
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.IS_{}_INVERTED({}),""".format(param, is_inverted)
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verilog_ports += """
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.{}({}),""".format(param, luts.get_next_output_net())
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verilog_attr = verilog_attr.rstrip(",")
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verilog_attr += "\n)"
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print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
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print(
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"""GTXE2_CHANNEL {attrs} {site} (
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{ports}
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);
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""".format(
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attrs=verilog_attr,
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site=tile_type.lower(),
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ports=verilog_ports.rstrip(",")))
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params_list.append(params)
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params_dict["params"] = params_list
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primitives_list.append(params_dict)
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for l in luts.create_wires_and_luts():
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print(l)
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print("endmodule")
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with open('params.json', 'w') as f:
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json.dump(primitives_list, f, indent=2)
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if __name__ == '__main__':
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main()
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