mirror of https://github.com/openXC7/prjxray.git
571 lines
16 KiB
Python
571 lines
16 KiB
Python
""" Emits top.v's for various BUFHCE routing inputs. """
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import os
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import random
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import re
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.db import Database
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from prjxray.lut_maker import LutMaker
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from io import StringIO
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CMT_XY_FUN = util.create_xy_fun(prefix='')
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BUFGCTRL_XY_FUN = util.create_xy_fun('BUFGCTRL_')
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BUFHCE_XY_FUN = util.create_xy_fun('BUFHCE_')
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def gen_sites(desired_site_type):
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site, site_type in gridinfo.sites.items():
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if site_type == desired_site_type:
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yield loc, gridinfo.tile_type, site
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def gen_bufhce_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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sites = []
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for site, site_type in gridinfo.sites.items():
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if site_type == 'BUFHCE':
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sites.append(site)
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if sites:
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yield tile_name, sorted(sites)
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def read_site_to_cmt():
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""" Yields clock sources and which CMT they route within. """
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with open(os.path.join(os.getenv('FUZDIR'), 'build',
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'cmt_regions.csv')) as f:
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for l in f:
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site, cmt = l.strip().split(',')
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yield (site, cmt)
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class ClockSources(object):
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""" Class for tracking clock sources.
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Some clock sources can be routed to any CMT, for these, cmt='ANY'.
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For clock sources that belong to a CMT, cmt should be set to the CMT of
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the source.
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"""
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def __init__(self):
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self.sources = {}
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self.merged_sources = {}
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self.source_to_cmt = {}
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self.used_sources_from_cmt = {}
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self.sources_by_loc = {}
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self.active_cmt_ports = {}
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def add_clock_source(self, source, cmt, loc=None):
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""" Adds a source from a specific CMT.
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cmt='ANY' indicates that this source can be routed to any CMT.
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"""
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if cmt not in self.sources:
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self.sources[cmt] = []
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self.sources[cmt].append(source)
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assert source not in self.source_to_cmt or self.source_to_cmt[
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source] == cmt, source
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self.source_to_cmt[source] = cmt
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self.add_bufg_clock_source(source, cmt, loc)
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def add_bufg_clock_source(self, source, cmt, loc):
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if loc not in self.sources_by_loc:
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self.sources_by_loc[loc] = []
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self.sources_by_loc[loc].append((cmt, source))
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def get_random_source(self, cmt):
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""" Get a random source that is routable to the specific CMT.
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get_random_source will return a source that is either cmt='ANY',
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cmt equal to the input CMT, or the adjecent CMT.
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"""
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if cmt not in self.merged_sources:
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choices = []
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if 'ANY' in self.sources:
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choices.extend(self.sources['ANY'])
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if cmt in self.sources:
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choices.extend(self.sources[cmt])
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x, y = CMT_XY_FUN(cmt)
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if x % 2 == 0:
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x += 1
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else:
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x -= 1
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paired_cmt = 'X{}Y{}'.format(x, y)
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if paired_cmt in self.sources:
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choices.extend(self.sources[paired_cmt])
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self.merged_sources[cmt] = choices
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if self.merged_sources[cmt]:
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source = random.choice(self.merged_sources[cmt])
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source_cmt = self.source_to_cmt[source]
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if source_cmt not in self.used_sources_from_cmt:
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self.used_sources_from_cmt[source_cmt] = set()
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self.used_sources_from_cmt[source_cmt].add(source)
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if source_cmt != 'ANY' and len(
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self.used_sources_from_cmt[source_cmt]) > 14:
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self.used_sources_from_cmt[source_cmt].remove(source)
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return None
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else:
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return source
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def get_bufg_source(self, loc, tile_type, site, todos, i_wire, used_only):
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bufg_sources = []
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top = '_TOP_' in tile_type
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bottom = '_BOT_' in tile_type
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assert top ^ bottom, tile_type
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if top:
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for src_loc, cmt_sources in self.sources_by_loc.items():
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if src_loc is None:
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continue
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if src_loc.grid_y <= loc.grid_y:
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bufg_sources.extend(cmt_sources)
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elif bottom:
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for src_loc, cmt_sources in self.sources_by_loc.items():
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if src_loc is None:
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continue
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if src_loc.grid_y > loc.grid_y:
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bufg_sources.extend(cmt_sources)
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# CLK_HROW_TOP_R_CK_BUFG_CASCO0 -> CLK_BUFG_BUFGCTRL0_I0
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# CLK_HROW_TOP_R_CK_BUFG_CASCO22 -> CLK_BUFG_BUFGCTRL11_I0
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# CLK_HROW_TOP_R_CK_BUFG_CASCO23 -> CLK_BUFG_BUFGCTRL11_I1
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# CLK_HROW_BOT_R_CK_BUFG_CASCO27 -> CLK_BUFG_BUFGCTRL13_I1
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x, y = BUFGCTRL_XY_FUN(site)
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assert x == 0
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y = y % 16
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assert i_wire in [0, 1], i_wire
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casco_wire = '{tile_type}_CK_BUFG_CASCO{casco_idx}'.format(
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tile_type=tile_type.replace('BUFG', 'HROW'),
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casco_idx=(y * 2 + i_wire))
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if casco_wire not in todos:
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return None
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target_wires = []
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need_bufr = False
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for src_wire in todos[casco_wire]:
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if 'BUFRCLK' in src_wire:
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need_bufr = True
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break
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for cmt, wire in bufg_sources:
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if 'BUFR' in wire:
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if need_bufr:
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target_wires.append((cmt, wire))
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else:
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target_wires.append((cmt, wire))
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random.shuffle(target_wires)
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for cmt, source in target_wires:
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if cmt == 'ANY':
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return source
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else:
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# Make sure to not try to import move than 14 sources from
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# the CMT, there is limited routing.
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if cmt not in self.used_sources_from_cmt:
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self.used_sources_from_cmt[cmt] = set()
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if source in self.used_sources_from_cmt[cmt]:
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return source
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elif used_only:
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continue
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if len(self.used_sources_from_cmt[cmt]) < 14:
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self.used_sources_from_cmt[cmt].add(source)
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return source
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else:
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continue
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return None
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def check_allowed(mmcm_pll_dir, cmt):
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""" Check whether the CMT specified is in the allowed direction.
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This function is designed to bias sources to either the left or right
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input lines.
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"""
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if mmcm_pll_dir == 'BOTH':
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return True
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elif mmcm_pll_dir == 'ODD':
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x, y = CMT_XY_FUN(cmt)
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return (x & 1) == 1
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elif mmcm_pll_dir == 'EVEN':
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x, y = CMT_XY_FUN(cmt)
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return (x & 1) == 0
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elif mmcm_pll_dir == 'NONE':
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return False
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else:
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assert False, mmcm_pll_dir
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def read_todo():
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dsts = {}
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with open(os.path.join('..', 'todo_all.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if dst not in dsts:
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dsts[dst] = set()
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dsts[dst].add(src)
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return dsts
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def need_int_connections(todos):
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for srcs in todos.values():
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for src in srcs:
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if re.search('INT_._.', src):
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return True
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return False
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def bufhce_in_todo(todos, site):
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if 'BUFHCE' in site:
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# CLK_HROW_CK_MUX_OUT_R9 -> X1Y9
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# CLK_HROW_CK_MUX_OUT_L11 -> X0Y35
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x, y = BUFHCE_XY_FUN(site)
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y = y % 12
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if x == 0:
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lr = 'L'
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elif x == 1:
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lr = 'R'
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else:
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assert False, x
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return 'CLK_HROW_CK_MUX_OUT_{lr}{y}'.format(lr=lr, y=y) in todos
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else:
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return True
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def need_gclk_connection(todos, site):
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x, y = BUFGCTRL_XY_FUN(site)
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assert x == 0
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src_wire = 'CLK_HROW_R_CK_GCLK{}'.format(y)
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for srcs in todos.values():
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if src_wire in srcs:
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return True
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return False
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def only_gclk_left(todos):
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for srcs in todos.values():
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for src in srcs:
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if 'GCLK' not in src:
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return False
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return True
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def main():
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"""
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BUFHCE's can be driven from:
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MMCME2_ADV
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PLLE2_ADV
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BUFGCTRL
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Local INT connect
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"""
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print('''
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module top();
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''')
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site_to_cmt = dict(read_site_to_cmt())
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clock_sources = ClockSources()
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# To ensure that all left or right sources are used, sometimes only MMCM/PLL
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# sources are allowed. The force of ODD/EVEN/BOTH further biases the
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# clock sources to the left or right column inputs.
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mmcm_pll_only = random.randint(0, 1)
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mmcm_pll_dir = random.choice(('ODD', 'EVEN', 'BOTH', 'NONE'))
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todos = read_todo()
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if only_gclk_left(todos):
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mmcm_pll_dir = 'NONE'
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if not mmcm_pll_only:
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if need_int_connections(todos):
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for _ in range(10):
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clock_sources.add_clock_source('one', 'ANY')
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clock_sources.add_clock_source('zero', 'ANY')
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print("""
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wire zero = 0;
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wire one = 1;""")
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for loc, _, site in gen_sites('MMCME2_ADV'):
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mmcm_clocks = [
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'mmcm_clock_{site}_{idx}'.format(site=site, idx=idx)
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for idx in range(13)
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]
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if check_allowed(mmcm_pll_dir, site_to_cmt[site]):
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for clk in mmcm_clocks:
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clock_sources.add_clock_source(clk, site_to_cmt[site], loc)
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print(
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"""
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wire {c0}, {c1}, {c2}, {c3}, {c4}, {c5};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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MMCME2_ADV pll_{site} (
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.CLKOUT0({c0}),
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.CLKOUT0B({c1}),
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.CLKOUT1({c2}),
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.CLKOUT1B({c3}),
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.CLKOUT2({c4}),
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.CLKOUT2B({c5}),
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.CLKOUT3({c6}),
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.CLKOUT3B({c7}),
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.CLKOUT4({c8}),
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.CLKOUT5({c9}),
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.CLKOUT6({c10}),
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.CLKFBOUT({c11}),
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.CLKFBOUTB({c12})
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);
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""".format(
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site=site,
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c0=mmcm_clocks[0],
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c1=mmcm_clocks[1],
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c2=mmcm_clocks[2],
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c3=mmcm_clocks[3],
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c4=mmcm_clocks[4],
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c5=mmcm_clocks[5],
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c6=mmcm_clocks[6],
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c7=mmcm_clocks[7],
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c8=mmcm_clocks[8],
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c9=mmcm_clocks[9],
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c10=mmcm_clocks[10],
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c11=mmcm_clocks[11],
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c12=mmcm_clocks[12],
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))
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for loc, _, site in gen_sites('PLLE2_ADV'):
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pll_clocks = [
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'pll_clock_{site}_{idx}'.format(site=site, idx=idx)
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for idx in range(6)
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]
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if check_allowed(mmcm_pll_dir, site_to_cmt[site]):
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for clk in pll_clocks:
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clock_sources.add_clock_source(clk, site_to_cmt[site], loc)
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print(
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"""
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wire {c0}, {c1}, {c2}, {c3}, {c4}, {c5};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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PLLE2_ADV pll_{site} (
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.CLKOUT0({c0}),
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.CLKOUT1({c1}),
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.CLKOUT2({c2}),
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.CLKOUT3({c3}),
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.CLKOUT4({c4}),
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.CLKOUT5({c5})
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);
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""".format(
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site=site,
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c0=pll_clocks[0],
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c1=pll_clocks[1],
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c2=pll_clocks[2],
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c3=pll_clocks[3],
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c4=pll_clocks[4],
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c5=pll_clocks[5],
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))
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for loc, _, site in gen_sites('BUFR'):
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clock_sources.add_bufg_clock_source(
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'O_{site}'.format(site=site), site_to_cmt[site], loc)
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print(
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"""
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wire O_{site};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFR bufr_{site} (
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.O(O_{site})
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);""".format(site=site))
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luts = LutMaker()
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bufhs = StringIO()
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bufgs = StringIO()
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gclks = []
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for _, _, site in sorted(gen_sites("BUFGCTRL"),
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key=lambda x: BUFGCTRL_XY_FUN(x[2])):
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wire_name = 'gclk_{}'.format(site)
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gclks.append(wire_name)
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include_source = True
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if mmcm_pll_only:
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include_source = False
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elif only_gclk_left(todos):
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include_source = need_gclk_connection(todos, site)
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if include_source:
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clock_sources.add_clock_source(wire_name, 'ANY')
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print("""
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wire {wire_name};
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""".format(wire_name=wire_name))
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print(
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"""
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wire I1_{site};
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wire I0_{site};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFGCTRL bufg_{site} (
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.O({wire_name}),
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.S1({s1net}),
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.S0({s0net}),
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.IGNORE1({ignore1net}),
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.IGNORE0({ignore0net}),
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.I1(I1_{site}),
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.I0(I0_{site}),
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.CE1({ce1net}),
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.CE0({ce0net})
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);
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""".format(
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site=site,
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wire_name=wire_name,
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s1net=luts.get_next_output_net(),
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s0net=luts.get_next_output_net(),
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ignore1net=luts.get_next_output_net(),
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ignore0net=luts.get_next_output_net(),
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ce1net=luts.get_next_output_net(),
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ce0net=luts.get_next_output_net(),
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),
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file=bufgs)
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any_bufhce = False
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for tile_name, sites in gen_bufhce_sites():
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for site in sites:
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if not bufhce_in_todo(todos, site):
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continue
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any_bufhce = True
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print(
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"""
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wire I_{site};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFHCE buf_{site} (
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.I(I_{site})
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);
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""".format(site=site, ),
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file=bufhs)
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if random.random() > .05:
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wire_name = clock_sources.get_random_source(site_to_cmt[site])
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if wire_name is None:
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continue
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print(
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"""
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assign I_{site} = {wire_name};""".format(
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site=site,
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wire_name=wire_name,
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),
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file=bufhs)
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if not any_bufhce:
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for tile_name, sites in gen_bufhce_sites():
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for site in sites:
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print(
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"""
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFHCE #(
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.INIT_OUT({INIT_OUT}),
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.CE_TYPE({CE_TYPE}),
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.IS_CE_INVERTED({IS_CE_INVERTED})
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) buf_{site} (
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.I({wire_name})
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);
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""".format(
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INIT_OUT=random.randint(0, 1),
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CE_TYPE=verilog.quote(
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random.choice(('SYNC', 'ASYNC'))),
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IS_CE_INVERTED=random.randint(0, 1),
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site=site,
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wire_name=gclks[0],
|
|
))
|
|
break
|
|
break
|
|
|
|
for l in luts.create_wires_and_luts():
|
|
print(l)
|
|
|
|
print(bufhs.getvalue())
|
|
print(bufgs.getvalue())
|
|
|
|
used_only = random.random() < .25
|
|
|
|
for loc, tile_type, site in sorted(gen_sites("BUFGCTRL"),
|
|
key=lambda x: BUFGCTRL_XY_FUN(x[2])):
|
|
if random.randint(0, 1):
|
|
wire_name = clock_sources.get_bufg_source(
|
|
loc, tile_type, site, todos, 1, used_only)
|
|
if wire_name is not None:
|
|
print(
|
|
"""
|
|
assign I1_{site} = {wire_name};""".format(
|
|
site=site,
|
|
wire_name=wire_name,
|
|
))
|
|
|
|
if random.randint(0, 1):
|
|
wire_name = clock_sources.get_bufg_source(
|
|
loc, tile_type, site, todos, 0, used_only)
|
|
if wire_name is not None:
|
|
print(
|
|
"""
|
|
assign I0_{site} = {wire_name};""".format(
|
|
site=site,
|
|
wire_name=wire_name,
|
|
))
|
|
|
|
print("endmodule")
|
|
|
|
|
|
if __name__ == '__main__':
|
|
main()
|