mirror of https://github.com/openXC7/prjxray.git
191 lines
7.3 KiB
Python
191 lines
7.3 KiB
Python
#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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import json
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def handle_data_width(segmk, d):
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if 'DATA_WIDTH' not in d:
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return
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if d['DATA_RATE'] == 'DDR':
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return
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for opt in [2, 3, 4, 5, 6, 7, 8, 10, 14]:
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segmk.add_site_tag(
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d['site'], 'ISERDES.DATA_WIDTH.{}'.format(opt),
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d['DATA_WIDTH'] == opt)
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def handle_data_rate(segmk, d):
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if 'DATA_WIDTH' not in d:
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return
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for opt in ['SDR', 'DDR']:
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segmk.add_site_tag(
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d['site'], 'ISERDES.DATA_RATE.{}'.format(opt),
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verilog.unquote(d['DATA_RATE']) == opt)
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def main():
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print("Loading tags")
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segmk = Segmaker("design.bits")
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with open('params.jl', 'r') as f:
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design = json.load(f)
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for d in design:
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site = d['site']
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handle_data_width(segmk, d)
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handle_data_rate(segmk, d)
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if 'INTERFACE_TYPE' in d:
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for opt in (
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'MEMORY',
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'MEMORY_DDR3',
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'MEMORY_QDR',
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'NETWORKING',
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'OVERSAMPLE',
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):
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segmk.add_site_tag(
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site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt),
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opt == verilog.unquote(d['INTERFACE_TYPE']))
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if d['iddr_mux_config'] != 'none':
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segmk.add_site_tag(site, 'IFF.ZINIT_Q1', not d['INIT_Q1'])
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segmk.add_site_tag(site, 'IFF.ZINIT_Q2', not d['INIT_Q2'])
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if 'INIT_Q3' in d:
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segmk.add_site_tag(site, 'IFF.ZINIT_Q3', not d['INIT_Q3'])
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segmk.add_site_tag(site, 'IFF.ZINIT_Q4', not d['INIT_Q4'])
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segmk.add_site_tag(
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site, 'IFF.ZSRVAL_Q1', not d['SRVAL_Q1'])
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segmk.add_site_tag(
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site, 'IFF.ZSRVAL_Q2', not d['SRVAL_Q2'])
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segmk.add_site_tag(
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site, 'IFF.ZSRVAL_Q3', not d['SRVAL_Q3'])
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segmk.add_site_tag(
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site, 'IFF.ZSRVAL_Q4', not d['SRVAL_Q4'])
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if 'IS_CLK_INVERTED' in d:
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if verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY_DDR3':
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segmk.add_site_tag(
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site, 'IFF.ZINV_CLK', not d['IS_CLK_INVERTED'])
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segmk.add_site_tag(
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site, 'IFF.ZINV_CLKB', not d['IS_CLKB_INVERTED'])
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segmk.add_site_tag(
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site, 'IFF.ZINV_CLK_XOR',
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d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED'])
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segmk.add_site_tag(
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site, 'IFF.ZINV_CLK_NXOR',
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not (d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED']))
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segmk.add_site_tag(
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site, 'IFF.ZINV_CLK_OR', d['IS_CLK_INVERTED']
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or d['IS_CLKB_INVERTED'])
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segmk.add_site_tag(
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site, 'IFF.ZINV_CLK_NOR', not (
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d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED']))
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segmk.add_site_tag(
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site, 'IFF.ZINV_CLK_AND', d['IS_CLK_INVERTED']
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and d['IS_CLKB_INVERTED'])
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segmk.add_site_tag(
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site, 'IFF.ZINV_CLK_NAND', not (
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d['IS_CLK_INVERTED']
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and d['IS_CLKB_INVERTED']))
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if 'IS_OCLK_INVERTED' in d:
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segmk.add_site_tag(
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site, 'IFF.ZINV_OCLK', not d['IS_OCLK_INVERTED'])
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if 'IS_C_INVERTED' in d:
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segmk.add_site_tag(
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site, 'IFF.ZINV_C', not d['IS_C_INVERTED'])
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segmk.add_site_tag(site, 'ZINV_D', not d['IS_D_INVERTED'])
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if 'SRTYPE' in d:
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for opt in ['ASYNC', 'SYNC']:
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segmk.add_site_tag(
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site, 'IFF.SRTYPE.{}'.format(opt),
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verilog.unquote(d['SRTYPE']) == opt)
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if 'DDR_CLK_EDGE' in d:
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for opt in ['OPPOSITE_EDGE', 'SAME_EDGE',
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'SAME_EDGE_PIPELINED']:
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segmk.add_site_tag(
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site, 'IFF.DDR_CLK_EDGE.{}'.format(opt),
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verilog.unquote(d['DDR_CLK_EDGE']) == opt)
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ofb_used = False
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if 'OFB_USED' in d and d['OFB_USED']:
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ofb_used = True
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if d['iddr_mux_config'] == 'direct':
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segmk.add_site_tag(site, 'IFFDELMUXE3.0', 0)
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segmk.add_site_tag(site, 'IFFDELMUXE3.1', 1)
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segmk.add_site_tag(site, 'IFFDELMUXE3.2', 0)
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if ofb_used:
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segmk.add_site_tag(site, 'IFFMUX.1', 1)
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segmk.add_site_tag(site, 'IFFMUX.0', 0)
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else:
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segmk.add_site_tag(site, 'IFFMUX.1', 0)
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segmk.add_site_tag(site, 'IFFMUX.0', 1)
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elif d['iddr_mux_config'] == 'idelay':
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segmk.add_site_tag(site, 'IFFDELMUXE3.0', 1)
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segmk.add_site_tag(site, 'IFFDELMUXE3.1', 0)
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segmk.add_site_tag(site, 'IFFDELMUXE3.2', 0)
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if ofb_used:
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segmk.add_site_tag(site, 'IFFMUX.1', 1)
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segmk.add_site_tag(site, 'IFFMUX.0', 0)
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else:
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segmk.add_site_tag(site, 'IFFMUX.1', 0)
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segmk.add_site_tag(site, 'IFFMUX.0', 1)
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elif d['iddr_mux_config'] == 'none':
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segmk.add_site_tag(site, 'IFFDELMUXE3.0', 0)
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segmk.add_site_tag(site, 'IFFDELMUXE3.1', 0)
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segmk.add_site_tag(site, 'IFFDELMUXE3.2', 0)
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else:
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assert False, d['mux_config']
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if d['mux_config'] == 'direct':
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segmk.add_site_tag(site, 'IDELMUXE3.0', 0)
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segmk.add_site_tag(site, 'IDELMUXE3.1', 1)
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segmk.add_site_tag(site, 'IDELMUXE3.2', 0)
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if ofb_used:
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segmk.add_site_tag(site, 'IMUX.1', 1)
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segmk.add_site_tag(site, 'IMUX.0', 0)
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else:
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segmk.add_site_tag(site, 'IMUX.1', 0)
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segmk.add_site_tag(site, 'IMUX.0', 1)
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elif d['mux_config'] == 'idelay':
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segmk.add_site_tag(site, 'IDELMUXE3.0', 1)
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segmk.add_site_tag(site, 'IDELMUXE3.1', 0)
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segmk.add_site_tag(site, 'IDELMUXE3.2', 0)
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if ofb_used:
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segmk.add_site_tag(site, 'IMUX.1', 1)
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segmk.add_site_tag(site, 'IMUX.0', 0)
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else:
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segmk.add_site_tag(site, 'IMUX.1', 0)
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segmk.add_site_tag(site, 'IMUX.0', 1)
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elif d['mux_config'] == 'none':
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segmk.add_site_tag(site, 'IDELMUXE3.0', 0)
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segmk.add_site_tag(site, 'IDELMUXE3.1', 0)
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segmk.add_site_tag(site, 'IDELMUXE3.2', 0)
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else:
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assert False, d['mux_config']
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segmk.compile()
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segmk.write(allow_empty=True)
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if __name__ == "__main__":
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main()
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