mirror of https://github.com/openXC7/prjxray.git
40 lines
894 B
Python
40 lines
894 B
Python
#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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def bus_tags(segmk, ps, site):
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for param, tagname in [('CLKOUT0_DIVIDE', 'ZCLKOUT0_DIVIDE')]:
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# 1-128 => 0-127 for actual 7 bit value
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paramadj = int(ps[param]) - 1
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bitstr = [int(x) for x in "{0:07b}".format(paramadj)[::-1]]
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# FIXME: only bits 0 and 1 resolving
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# for i in range(7):
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for i in range(2):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
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def run():
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segmk = Segmaker("design.bits")
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print("Loading tags")
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f = open('params.jl', 'r')
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f.readline()
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for l in f:
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j = json.loads(l)
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ps = j['params']
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assert j['module'] == 'my_PLLE2_ADV'
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site = verilog.unquote(ps['LOC'])
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bus_tags(segmk, ps, site)
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segmk.compile()
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segmk.write()
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run()
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