mirror of https://github.com/openXC7/prjxray.git
149 lines
5.0 KiB
Python
149 lines
5.0 KiB
Python
#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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from prjxray import segmaker
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from prjxray import verilog
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import os
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import json
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def bitfilter(frame, word):
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if frame < 26:
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return False
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return True
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def mk_drive_opt(iostandard, drive):
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return '{}.DRIVE.I{}'.format(iostandard, drive)
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def skip_broken_tiles(d):
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""" Skip tiles that appear to have bits always set.
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This is likely caused by a defect?
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"""
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if os.getenv('XRAY_DATABASE') == 'artix7' and d['tile'] == 'LIOB33_X0Y43':
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return True
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return False
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def drives_for_iostandard(iostandard):
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if iostandard in ['LVTTL', 'LVCMOS18']:
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drives = [4, 8, 12, 16, 24]
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elif iostandard == 'LVCMOS12':
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drives = [4, 8, 12]
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else:
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drives = [4, 8, 12, 16]
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return drives
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STEPDOWN_IOSTANDARDS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18']
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def main():
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print("Loading tags")
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segmk = Segmaker("design.bits")
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'''
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port,site,tile,pin,slew,drive,pulltype
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di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
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di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
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'''
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with open('params.jl', 'r') as f:
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design = json.load(f)
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for d in design:
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site = d['site']
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if skip_broken_tiles(d):
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continue
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iostandard = verilog.unquote(d['IOSTANDARD'])
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stepdown = iostandard in STEPDOWN_IOSTANDARDS
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segmk.add_site_tag(site, '_'.join(STEPDOWN_IOSTANDARDS), stepdown)
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if d['type'] is None:
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
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for drive in drives_for_iostandard(iostandard):
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 0)
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elif d['type'] == 'IBUF':
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
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for drive in drives_for_iostandard(iostandard):
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 1)
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elif d['type'] == 'OBUF':
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
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for drive in drives_for_iostandard(iostandard):
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if drive == d['DRIVE']:
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 1)
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else:
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 0)
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elif d['type'] == 'IOBUF_INTERMDISABLE':
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segmk.add_site_tag(site, 'INOUT', 1)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
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if d['type'] is not None:
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segmaker.add_site_group_zero(
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segmk, site, "PULLTYPE.",
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("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
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verilog.unquote(d['PULLTYPE']))
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if d['type'] == 'IBUF' or d['type'] is None:
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continue
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drive_opts = set()
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for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
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"LVCMOS12", 'LVTTL'):
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for drive_opt in ("4", "8", "12", "16", "24"):
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if drive_opt == "16" and opt == "LVCMOS12":
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continue
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if drive_opt == "24" and opt not in ["LVCMOS18", 'LVTTL']:
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continue
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drive_opts.add(mk_drive_opt(opt, drive_opt))
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segmaker.add_site_group_zero(
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segmk, site, '', drive_opts, mk_drive_opt('LVCMOS25', '12'),
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mk_drive_opt(iostandard, d['DRIVE']))
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segmaker.add_site_group_zero(
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segmk, site, "SLEW.", ("SLOW", "FAST"), "FAST",
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verilog.unquote(d['SLEW']))
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if 'ibufdisable_wire' in d:
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segmk.add_site_tag(
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site, 'IBUFDISABLE.I', d['ibufdisable_wire'] != '0')
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if 'intermdisable_wire' in d:
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segmk.add_site_tag(
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site, 'INTERMDISABLE.I', d['intermdisable_wire'] != '0')
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segmk.compile(bitfilter=bitfilter)
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segmk.write(allow_empty=True)
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if __name__ == "__main__":
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main()
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