mirror of https://github.com/openXC7/prjxray.git
61 lines
1.4 KiB
Tcl
61 lines
1.4 KiB
Tcl
source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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set fp [open top.txt]
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set int_tiles [split [read $fp] "\n"]
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close $fp
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set fp [open design.txt]
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set pips [split [read $fp] "\n"]
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close $fp
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set found_int_tiles {}
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foreach pip $pips {
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set parts [split $pip " "]
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set tile_idx [lsearch -exact $int_tiles [lindex $parts 0]]
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if {$tile_idx == -1} {
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continue
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}
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set tile [lindex $int_tiles $tile_idx]
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set pip_of_interest "$tile/INT_L.EL1END1->>EE2BEG1"
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if { $pip_of_interest == [lindex $parts 1] } {
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lappend found_int_tiles $tile
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}
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}
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set fp [open params.csv "w"]
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puts $fp "tile,val"
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foreach tile $int_tiles {
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if {$tile == ""} {
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continue
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}
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set pip_active [lsearch -exact $found_int_tiles $tile]
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if {$pip_active != -1} {
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puts $fp "$tile,1"
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} else {
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puts $fp "$tile,0"
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}
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}
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close $fp
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}
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run
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