mirror of https://github.com/openXC7/prjxray.git
62 lines
2.2 KiB
Tcl
62 lines
2.2 KiB
Tcl
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create_project -force -part $::env(XRAY_PART) design_fdre design_fdre
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read_verilog top_ref.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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set_property LOC RAMB36_X0Y21 [get_cells ram]
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route_design
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#set_property IS_ROUTE_FIXED 1 [get_nets -hierarchical]
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set_property IS_LOC_FIXED 1 [get_cells -hierarchical]
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set_property IS_BEL_FIXED 1 [get_cells -hierarchical]
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write_xdc -force fixed.xdc
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write_checkpoint -force design_ref.dcp
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write_bitstream -force design_ref.bit
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close_project
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foreach variant {CLKARDCLK_INV CLKBWRCLK_INV ENARDEN_INV ENBWREN_INV RSTRAMARSTRAM_INV RSTRAMB_INV RSTREGARSTREG_INV RSTREGB_INV RAM_MODE_SDP WRITE_MODE_A_NC WRITE_MODE_A_RF} {
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create_project -force -part $::env(XRAY_PART) design_${variant} design_${variant}
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read_verilog top_${variant}.v
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read_xdc fixed.xdc
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synth_design -top top
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if {0} {
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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}
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place_design
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route_design
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write_checkpoint -force design_${variant}.dcp
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write_bitstream -force design_${variant}.bit
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close_project
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}
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