mirror of https://github.com/openXC7/prjxray.git
35 lines
736 B
Python
35 lines
736 B
Python
#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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segmk = Segmaker("design.bits", verbose=True)
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print("Loading tags")
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f = open('params.jl', 'r')
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f.readline()
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for l in f:
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j = json.loads(l)
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ps = j['params']
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assert j['module'] == 'my_RAMB36E1'
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site = verilog.unquote(ps['LOC'])
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ks = [
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'IS_CLKARDCLK_INVERTED',
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'IS_CLKBWRCLK_INVERTED',
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'IS_ENARDEN_INVERTED',
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'IS_ENBWREN_INVERTED',
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'IS_RSTRAMARSTRAM_INVERTED',
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'IS_RSTRAMB_INVERTED',
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'IS_RSTREGARSTREG_INVERTED',
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'IS_RSTREGB_INVERTED',
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]
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for k in ks:
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segmk.add_site_tag(site, k, verilog.parsei(ps[k]))
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segmk.compile()
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segmk.write()
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