mirror of https://github.com/openXC7/prjxray.git
525 lines
21 KiB
Python
Executable File
525 lines
21 KiB
Python
Executable File
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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from __future__ import print_function
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import fasm
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import argparse
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import json
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import os
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import os.path
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import csv
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from collections import defaultdict
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from prjxray import fasm_assembler, util
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from prjxray.db import Database
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from prjxray.roi import Roi
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from prjxray.util import OpenSafeFile
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import sys
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def eprint(*args, **kwargs):
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print(*args, file=sys.stderr, **kwargs)
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class FASMSyntaxError(SyntaxError):
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pass
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def dump_frames_verbose(frames):
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print()
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print("Frames: %d" % len(frames))
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for addr in sorted(frames.keys()):
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words = frames[addr]
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print(
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'0x%08X ' % addr + ', '.join(['0x%08X' % w for w in words]) +
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'...')
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def dump_frames_sparse(frames):
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print()
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print("Frames: %d" % len(frames))
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for addr in sorted(frames.keys()):
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words = frames[addr]
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# Skip frames without filled words
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for w in words:
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if w:
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break
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else:
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continue
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print('Frame @ 0x%08X' % addr)
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for i, w in enumerate(words):
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if w:
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print(' % 3d: 0x%08X' % (i, w))
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def dump_frm(f, frames):
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'''Write a .frm file given a list of frames, each containing a list of 101 32 bit words'''
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for addr in sorted(frames.keys()):
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words = frames[addr]
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f.write(
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'0x%08X ' % addr + ','.join(['0x%08X' % w for w in words]) + '\n')
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def find_pudc_b(db):
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""" Find PUDC_B pin func in grid, and return the tile and site prefix.
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The PUDC_B pin is a special 7-series pin that controls unused pin pullup.
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If the PUDC_B is unused, it is configured as an input with a PULLUP.
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"""
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grid = db.grid()
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pudc_b_tile_site = None
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for tile in grid.tiles():
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gridinfo = grid.gridinfo_at_tilename(tile)
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for site, pin_function in gridinfo.pin_functions.items():
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if 'PUDC_B' in pin_function:
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assert pudc_b_tile_site == None, (
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pudc_b_tile_site, (tile, site))
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iob_y = int(site[-1]) % 2
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pudc_b_tile_site = (tile, 'IOB_Y{}'.format(iob_y))
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return pudc_b_tile_site
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def get_iob_sites(db, tile_name):
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"""
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Yields prjxray site names for given IOB tile name
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"""
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grid = db.grid()
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gridinfo = grid.gridinfo_at_tilename(tile_name)
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for site in gridinfo.sites:
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site_y = int(site[-1]) % 2
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yield "IOB_Y{}".format(site_y)
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def run(
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db_root,
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part,
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filename_in,
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f_out,
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sparse=False,
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roi=None,
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debug=False,
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emit_pudc_b_pullup=False):
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db = Database(db_root, part)
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assembler = fasm_assembler.FasmAssembler(db)
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set_features = set()
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def feature_callback(feature):
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set_features.add(feature)
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assembler.set_feature_callback(feature_callback)
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# Build mapping of tile to IO bank
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tile_to_bank = {}
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bank_to_tile = defaultdict(lambda: set())
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if part is not None:
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with OpenSafeFile(os.path.join(db_root, part, "package_pins.csv"), "r") as fp:
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reader = csv.DictReader(fp)
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package_pins = [l for l in reader]
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with OpenSafeFile(os.path.join(db_root, part, "part.json"), "r") as fp:
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part_data = json.load(fp)
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# The IO-bank "anchor" tile prefix differs per family. kintex7/artix7
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# use HR-bank IOLOGIC and therefore HCLK_IOI3. virtex7 HP-only parts
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# (e.g. xc7vx485tffg1761-2) use HCLK_IOI. Probe the grid for whichever
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# one actually exists; if neither, skip this bank-anchor altogether
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# rather than queueing a KeyError for downstream lookups.
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for bank, loc in part_data["iobanks"].items():
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for prefix in ("HCLK_IOI3_", "HCLK_IOI_"):
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tile = prefix + loc
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try:
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db.grid().gridinfo_at_tilename(tile)
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except KeyError:
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continue
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bank_to_tile[bank].add(tile)
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tile_to_bank[tile] = bank
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break
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for pin in package_pins:
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bank_to_tile[pin["bank"]].add(pin["tile"])
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tile_to_bank[pin["tile"]] = pin["bank"]
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# Resolve PUDC_B site unconditionally — we need the tile name later in the
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# HP-bank glue walk to skip it (Vivado does not set IBUF_HP_BANK_GLUE on
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# the PUDC_B tile even though our heuristic would).
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pudc_b_tile_site = find_pudc_b(db) if part is not None else None
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if emit_pudc_b_pullup:
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pudc_b_in_use = False
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def check_for_pudc_b(set_feature):
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feature_callback(set_feature)
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parts = set_feature.feature.split('.')
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if parts[0] == pudc_b_tile_site[0] and parts[
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1] == pudc_b_tile_site[1]:
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nonlocal pudc_b_in_use
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pudc_b_in_use = True
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if pudc_b_tile_site is not None:
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assembler.set_feature_callback(check_for_pudc_b)
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extra_features = []
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if roi:
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with OpenSafeFile(roi) as f:
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roi_j = json.load(f)
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x1 = roi_j['info']['GRID_X_MIN']
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x2 = roi_j['info']['GRID_X_MAX']
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y1 = roi_j['info']['GRID_Y_MIN']
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y2 = roi_j['info']['GRID_Y_MAX']
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assembler.mark_roi_frames(Roi(db=db, x1=x1, x2=x2, y1=y1, y2=y2))
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if 'required_features' in roi_j:
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extra_features = list(
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fasm.parse_fasm_string('\n'.join(roi_j['required_features'])))
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# Get required extra features for the part
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required_features = db.get_required_fasm_features(part)
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extra_features += list(
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fasm.parse_fasm_string('\n'.join(required_features)))
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assembler.parse_fasm_filename(filename_in, extra_features=extra_features)
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if emit_pudc_b_pullup and not pudc_b_in_use and pudc_b_tile_site is not None:
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# Enable IN-only and PULLUP on PUDC_B IOB.
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#
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# The set of IOSTANDARD aliases differs per family because HR-bank
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# (IOB33) silicon supports more standards than HP-bank (IOB18).
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# Pick the right alias by sniffing the tile name; the chosen alias
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# has to match a segbits entry exactly or fasm2frames will error.
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missing_features = []
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is_hp = pudc_b_tile_site[0].startswith('LIOB18') or \
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pudc_b_tile_site[0].startswith('RIOB18')
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if is_hp:
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# HP-bank (virtex7 xc7vx485tffg1761-2) — Vivado emits this exact
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# feature set on the PUDC_B IOB; the bits flow from segbits
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# entries on LVCMOS12_LVCMOS15.IN, LVCMOS12_LVCMOS15_LVCMOS18.IN,
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# the long IN_ONLY alias, two SLEW.SLOW aliases, the STEPDOWN
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# alias, PULLTYPE.PULLUP on Y0, and Y1's default-state SLEW/
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# STEPDOWN/PULLDOWN trio. Cross-referenced with a Vivado-built
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# rst_to_led reference bitstream.
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pudc_template = (
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"{tile}.{site}.LVCMOS12_LVCMOS15.IN\n"
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"{tile}.{site}.LVCMOS12_LVCMOS15_LVCMOS18.IN\n"
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"{tile}.{site}.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY\n"
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"{tile}.{site}.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW\n"
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"{tile}.{site}.LVCMOS12_LVCMOS15_LVCMOS18.SLEW.SLOW\n"
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"{tile}.{site}.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN\n"
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"{tile}.{site}.PULLTYPE.PULLUP\n"
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"{tile}.{partner}.LVCMOS12_LVCMOS15_LVCMOS18.SLEW.SLOW\n"
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"{tile}.{partner}.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN\n"
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"{tile}.{partner}.PULLTYPE.PULLDOWN\n"
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)
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partner = 'IOB_Y1' if pudc_b_tile_site[1] == 'IOB_Y0' else 'IOB_Y0'
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for line in fasm.parse_fasm_string(pudc_template.format(
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tile=pudc_b_tile_site[0],
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site=pudc_b_tile_site[1],
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partner=partner)):
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assembler.add_fasm_line(line, missing_features)
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else:
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# HR-bank (artix7/kintex7-HR/zynq7/spartan7) — original 3-line
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# template kept intact. TODO from the original code still
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# applies to K70T: it is known to be wrong but we have no
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# better data here.
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for line in fasm.parse_fasm_string("""
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{tile}.{site}.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY
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{tile}.{site}.LVCMOS25_LVCMOS33_LVTTL.IN
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{tile}.{site}.PULLTYPE.PULLUP
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""".format(
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tile=pudc_b_tile_site[0],
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site=pudc_b_tile_site[1],
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)):
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assembler.add_fasm_line(line, missing_features)
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if missing_features:
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raise fasm_assembler.FasmLookupError('\n'.join(missing_features))
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if part is not None:
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# Make a set of all used IOB tiles and sites. Look for the "STEPDOWN"
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# feature. If one is set for an IOB then set it for all other IOBs of
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# the same bank.
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stepdown_tags = defaultdict(lambda: set())
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stepdown_banks = set()
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used_iob_sites = set()
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for set_feature in set_features:
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if set_feature.value == 0:
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continue
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feature = set_feature.feature
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parts = feature.split(".")
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if len(parts) >= 3:
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tile, site, tag = feature.split(".", maxsplit=2)
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if "IOB33" in tile:
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used_iob_sites.add((
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tile,
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site,
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))
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# Store STEPDOWN related tags.
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if "STEPDOWN" in tag:
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bank = tile_to_bank[tile]
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stepdown_banks.add(bank)
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stepdown_tags[bank].add(tag)
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# Set the feature for unused IOBs, loop over all banks which were
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# observed to have the STEPDOWN feature set.
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missing_features = []
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for bank in stepdown_banks:
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for tile in bank_to_tile[bank]:
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# This is an IOB33 tile. Set the STEPDOWN feature in it but
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# only if it is unused.
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if "IOB33" in tile:
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for site in get_iob_sites(db, tile):
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if (tile, site) in used_iob_sites:
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continue
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for tag in stepdown_tags[bank]:
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feature = "{}.{}.{}".format(tile, site, tag)
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for line in fasm.parse_fasm_string(feature):
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assembler.add_fasm_line(line, missing_features)
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# On HR-bank parts the bank-anchor tile is HCLK_IOI3 and gets a
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# STEPDOWN feature; on virtex7 HP-only it is HCLK_IOI which has
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# the same STEPDOWN feature in our segbits.
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if "HCLK_IOI3" in tile or tile.startswith("HCLK_IOI_"):
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feature = "{}.STEPDOWN".format(tile)
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for line in fasm.parse_fasm_string(feature):
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assembler.add_fasm_line(line, missing_features)
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if missing_features:
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raise fasm_assembler.FasmLookupError('\n'.join(missing_features))
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# HP-bank (LIOB18/RIOB18) "bank-glue" auto-injection.
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# The HP-class output buffer (OUTBUF_DCIEN) needs three driver-enable
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# bits, and the HP-class input buffer (INBUF_DCIEN) needs one input-
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# enable bit. Vivado emits these implicitly for every used HP-bank
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# IOB; on HR-bank IOB33 the equivalent bits are factory-default so
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# were never captured in upstream prjxray. For round-trip parity on
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# virtex7 xc7vx485tffg1761-2 (HP-only) we inject the right tag
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# whenever any IOB feature is set on an HP-bank tile, mirroring the
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# STEPDOWN walk above.
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glue_missing = []
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liob_in_features = defaultdict(lambda: {'in': False, 'out': False, 'diff_in': False})
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for set_feature in set_features:
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if set_feature.value == 0:
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continue
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feature = set_feature.feature
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parts = feature.split(".")
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if len(parts) < 3:
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continue
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tile = parts[0]
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site = parts[1]
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tag = ".".join(parts[2:])
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if not (tile.startswith("LIOB18") or tile.startswith("RIOB18")):
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continue
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if site not in ("IOB_Y0", "IOB_Y1"):
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continue
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# Direction heuristic. Pure ".IN" / ".IN_ONLY" indicates IBUF.
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# ".DRIVE." is the only reliable OBUF marker — output drive
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# strength is meaningless for inputs. ".SLEW." and ".OUT" appear
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# on IBUF tiles too as bank-wide defaults (Vivado emits
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# SLEW.SLOW on every unused IOB), so they would mis-classify
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# IBUFs as IOBUFs and inject spurious OBUF_HP_BANK_GLUE bits.
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# ".IN_DIFF" indicates an IBUFDS (LVDS differential input).
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if "IN_DIFF" in tag:
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liob_in_features[(tile, site)]['diff_in'] = True
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elif "IN_ONLY" in tag or tag.endswith(".IN") or "IBUFDISABLE" in tag:
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liob_in_features[(tile, site)]['in'] = True
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if ".DRIVE." in tag:
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liob_in_features[(tile, site)]['out'] = True
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# Track whether the col-32 LIOB18 column has any Y1 OBUFs anywhere.
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# When it does, Vivado lights a 6-bit "DCI cascade + bank active"
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# pattern in INT_L_X32Y49 — the bottom-most INT_L tile of the X32
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# routing spine that serves the LIOB18 column. The same indicator
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# exists for the X110 (R-side IOB) column too, mirrored at
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# INT_R_X110Y49 — we'd add that when the first RIOB18 test design
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# asks for it.
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any_liob18_y1_obuf = False
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# PUDC_B's tile already gets its own IN/IN_ONLY/PULLUP/SLEW features
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# injected above; do NOT also fire the IBUF_HP_BANK_GLUE rule on it.
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# Empirically (Vivado-built rst_to_led ref) the PUDC_B tile does not
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# carry the bank-glue bit because the pullup is a "virtual" tie,
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# not a real IBUF placement.
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pudc_b_tile_name = pudc_b_tile_site[0] if pudc_b_tile_site else None
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for (tile, site), kind in liob_in_features.items():
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if tile == pudc_b_tile_name:
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continue
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# Both IOB_Y0 (master) and IOB_Y1 (slave) sites have HP_BANK_GLUE
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# patterns now. The Y1 OBUF rule was derived from the counter
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# design (LIOB18 tiles with two driving OBUFs) — Vivado emits an
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# extra 3 bits at rel 30_041 / 32_016 / 33_061 when Y1 has a
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# ".DRIVE." feature in addition to Y0.
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if kind['in']:
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feature = "{}.{}.IBUF_HP_BANK_GLUE".format(tile, site)
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for line in fasm.parse_fasm_string(feature):
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assembler.add_fasm_line(line, glue_missing)
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if kind['out']:
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feature = "{}.{}.OBUF_HP_BANK_GLUE".format(tile, site)
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for line in fasm.parse_fasm_string(feature):
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assembler.add_fasm_line(line, glue_missing)
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if kind['diff_in']:
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# IBUFDS — empirically Vivado lights a 7-bit pattern in the
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# IOB_Y0 (M-site) slot of the differential pair. Y1 is the
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# negative-half slave and reuses the silicon defaults, so
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# no separate Y1 rule is needed.
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feature = "{}.IOB_Y0.IBUFDS_BANK_GLUE".format(tile)
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for line in fasm.parse_fasm_string(feature):
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assembler.add_fasm_line(line, glue_missing)
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if kind['out'] and site == 'IOB_Y1' and tile.startswith('LIOB18_X81'):
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any_liob18_y1_obuf = True
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if any_liob18_y1_obuf:
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for tag in ('INT_L_X32Y49.IOB_COL_OBUF_CASCADE_Y1',
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'INT_L_X32Y49.IOB_COL_BANK_ACTIVE'):
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for line in fasm.parse_fasm_string(tag):
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assembler.add_fasm_line(line, glue_missing)
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# GFAN0 T-tie root glue. When the design has an OBUF whose T
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# input must be tied to GND through general routing (e.g. an
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# IBUF→OBUF passthrough where no SLICE FF Q drives the OBUF),
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# Vivado emits INT_L_X62Y73.GFAN0.GND_WIRE / .IMUX_L33.GFAN0
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# FASM features AND lights one extra silicon bit at
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# INT_L_X62Y83 minor 26 bit 18 — the "this GFAN tie route is
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# in use" marker for the col-62 routing spine. Only the c=62
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# column has been observed needing this glue (the counter
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# designs use FF-driven OBUFs and route GFAN0 through other
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# columns without triggering an analogous bit). The rule fires
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# only when an X62-column GFAN0.GND_WIRE feature appears.
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x62_gfan_tile = None
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for set_feature in set_features:
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if set_feature.value == 0:
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continue
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feat = set_feature.feature
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if not feat.startswith('INT_L_X62'):
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continue
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if 'GFAN0.GND_WIRE' in feat:
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# The mirror tile (Y+10) gets the glue bit. For
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# INT_L_X62Y73 → INT_L_X62Y83.
|
|
tile = feat.split('.')[0]
|
|
import re as _re
|
|
m = _re.match(r'(INT_L_X(\d+))Y(\d+)', tile)
|
|
if m:
|
|
x62_gfan_tile = 'INT_L_X{}Y{}'.format(m.group(2), int(m.group(3)) + 10)
|
|
break
|
|
|
|
if x62_gfan_tile:
|
|
feature = '{}.GFAN_TIE_ROOT_GLUE'.format(x62_gfan_tile)
|
|
for line in fasm.parse_fasm_string(feature):
|
|
assembler.add_fasm_line(line, glue_missing)
|
|
|
|
# HCLK_L per-BUFRCLK-channel "active" markers. Empirically Vivado
|
|
# sets one extra bit per HCLK_L tile per BUFR channel in use, at
|
|
# minor 1 bit 28+ch. Only BUFRCLK3 is observed today (the
|
|
# counter_sw_bufr design); when a kintex7 → virtex7 comparison
|
|
# design that uses BUFRCLK0/1/2 is built we can add those analogues
|
|
# to segbits_hclk_l.db with bits 01_28 / 01_29 / 01_30 respectively.
|
|
hclkl_bufrclk_seen = {} # (hclkl_tile) -> set of channel-ids in use
|
|
for set_feature in set_features:
|
|
if set_feature.value == 0:
|
|
continue
|
|
feat = set_feature.feature
|
|
parts = feat.split('.')
|
|
if len(parts) < 3:
|
|
continue
|
|
if not parts[0].startswith('HCLK_L'):
|
|
continue
|
|
# HCLK_L_X..Y...HCLK_LEAF_CLK_B_TOP/BOTL[0-5].HCLK_CK_BUFRCLK[0-3]
|
|
tag = '.'.join(parts[2:])
|
|
if 'HCLK_CK_BUFRCLK' not in tag:
|
|
continue
|
|
ch = tag.rsplit('HCLK_CK_BUFRCLK', 1)[1]
|
|
if ch.isdigit():
|
|
hclkl_bufrclk_seen.setdefault(parts[0], set()).add(int(ch))
|
|
|
|
for hclkl_tile, channels in hclkl_bufrclk_seen.items():
|
|
for ch in channels:
|
|
if ch != 3:
|
|
# Only BUFRCLK3 has segbits data so far; skip rest
|
|
# silently so the partial rule doesn't error.
|
|
continue
|
|
feature = '{}.HCLK_LEAF_BUFRCLK{}_ACTIVE'.format(hclkl_tile, ch)
|
|
for line in fasm.parse_fasm_string(feature):
|
|
assembler.add_fasm_line(line, glue_missing)
|
|
|
|
# glue_missing entries indicate the segbits don't carry the rule yet
|
|
# (e.g. partially-built database); fall through silently rather than
|
|
# erroring, so this auto-injection is a no-op on databases that
|
|
# haven't been bank-glue-annotated.
|
|
|
|
frames = assembler.get_frames(sparse=sparse)
|
|
|
|
if debug:
|
|
dump_frames_sparse(frames)
|
|
|
|
dump_frm(f_out, frames)
|
|
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description=
|
|
'Convert FPGA configuration description ("FPGA assembly") into binary frame equivalent'
|
|
)
|
|
|
|
util.db_root_arg(parser)
|
|
util.part_arg(parser)
|
|
parser.add_argument(
|
|
'--sparse', action='store_true', help="Don't zero fill all frames")
|
|
parser.add_argument(
|
|
'--roi',
|
|
help="ROI design.json file defining which tiles are within the ROI.")
|
|
parser.add_argument(
|
|
'--emit_pudc_b_pullup',
|
|
help="Emit an IBUF and PULLUP on the PUDC_B pin if unused",
|
|
action='store_true')
|
|
parser.add_argument(
|
|
'--debug', action='store_true', help="Print debug dump")
|
|
parser.add_argument('fn_in', help='Input FPGA assembly (.fasm) file')
|
|
parser.add_argument(
|
|
'fn_out',
|
|
default='/dev/stdout',
|
|
nargs='?',
|
|
help='Output FPGA frame (.frm) file')
|
|
|
|
args = parser.parse_args()
|
|
run(
|
|
db_root=args.db_root,
|
|
part=args.part,
|
|
filename_in=args.fn_in,
|
|
f_out=open(args.fn_out, 'w'),
|
|
sparse=args.sparse,
|
|
roi=args.roi,
|
|
debug=args.debug,
|
|
emit_pudc_b_pullup=args.emit_pudc_b_pullup)
|
|
|
|
|
|
if __name__ == '__main__':
|
|
main()
|