mirror of https://github.com/openXC7/prjxray.git
484 lines
16 KiB
Python
484 lines
16 KiB
Python
#!/usr/bin/env python3
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'''
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Historically we grouped data into "segments"
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These were a region of the bitstream that encoded one or more tiles
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However, this didn't scale with certain tiles like BRAM
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Some sites had multiple bitstream areas and also occupied multiple tiles
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Decoding was then shifted to instead describe how each title is encoded
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A post processing step verifies that two tiles don't reference the same bitstream area
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'''
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import os, sys, json, re
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# matches lib/include/prjxray/xilinx/xc7series/block_type.h
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block_type_i2s = {
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0: 'CLB_IO_CLK',
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1: 'BLOCK_RAM',
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2: 'CFG_CLB',
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# special...maybe should error until we know what it is?
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# 3: 'RESERVED',
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}
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def addr2btype(base_addr):
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'''
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Convert integer address to block type
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Table 5-24: Frame Address Register Description
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Bit Index: [25:23]
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https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
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"Valid block types are CLB, I/O, CLK ( 000 ), block RAM content ( 001 ), and CFG_CLB ( 010 ). A normal bitstream does not include type 011 ."
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'''
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block_type_i = (base_addr >> 23) & 0x7
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return block_type_i2s[block_type_i]
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def nolr(tile_type):
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'''
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Remove _L or _R suffix tile_type suffix, if present
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Ex: BRAM_INT_INTERFACE_L => BRAM_INT_INTERFACE
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Ex: VBRK => VBRK
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'''
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postfix = tile_type[-2:]
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if postfix in ('_L', '_R'):
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return tile_type[:-2]
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else:
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return tile_type
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def load_tiles(tiles_fn):
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'''
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"$type $tile $grid_x $grid_y $typed_sites"
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typed_sites: foreach t $site_types s $sites
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'''
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tiles = list()
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with open(tiles_fn) as f:
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for line in f:
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# CLBLM_L CLBLM_L_X10Y98 30 106 SLICEL SLICE_X13Y98 SLICEM SLICE_X12Y98
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record = line.split()
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tile_type, tile_name, grid_x, grid_y = record[0:4]
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grid_x, grid_y = int(grid_x), int(grid_y)
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sites = {}
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for i in range(4, len(record), 2):
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site_type, site_name = record[i:i + 2]
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sites[site_name] = site_type
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tile = {
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'type': tile_type,
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'name': tile_name,
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'grid_x': grid_x,
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'grid_y': grid_y,
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'sites': sites,
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}
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tiles.append(tile)
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return tiles
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def load_baseaddrs(deltas_fns):
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site_baseaddr = dict()
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for arg in deltas_fns:
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with open(arg) as f:
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line = f.read().strip()
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site = arg[7:-6]
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frame = int(line[5:5 + 8], 16)
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# was "0x%08x"
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site_baseaddr[site] = frame & ~0x7f
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return site_baseaddr
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def make_database(tiles):
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# tile database with X, Y, and list of sites
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# tile name as keys
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database = dict()
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for tile in tiles:
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database[tile["name"]] = {
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"type": tile["type"],
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"sites": tile["sites"],
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"grid_x": tile["grid_x"],
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"grid_y": tile["grid_y"],
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}
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return database
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def make_tile_baseaddrs(tiles, site_baseaddr, verbose=False):
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# Look up a base address by tile name
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tile_baseaddrs = dict()
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verbose and print('')
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for tile in tiles:
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for site_name in tile["sites"].keys():
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if site_name not in site_baseaddr:
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continue
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framebaseaddr = site_baseaddr[site_name]
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bt = addr2btype(framebaseaddr)
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tile_baseaddr = tile_baseaddrs.setdefault(tile["name"], {})
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if bt in tile_baseaddr:
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# actually lets just fail these, better to remove at tcl level to speed up processing
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assert 0, 'duplicate base address'
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assert tile_baseaddr[bt] == [framebaseaddr, 0]
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else:
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tile_baseaddr[bt] = [framebaseaddr, 0]
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verbose and print(
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"baseaddr: %s.%s @ %s.0x%08x" %
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(tile["name"], site_name, bt, framebaseaddr))
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return tile_baseaddrs
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def make_tiles_by_grid(tiles):
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# lookup tile names by (X, Y)
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tiles_by_grid = dict()
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for tile in tiles:
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tiles_by_grid[(tile["grid_x"], tile["grid_y"])] = tile["name"]
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return tiles_by_grid
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def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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'''
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Create segments data structure
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Indicates how tiles are related to bitstream locations
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Also modify database to annotate which segment the tiles belong to
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segments key examples:
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SEG_CLBLM_R_X13Y72
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SEG_BRAM3_L_X6Y85
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'''
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segments = dict()
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verbose and print('')
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for tile_name, tile_data in database.items():
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tile_type = tile_data["type"]
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grid_x = tile_data["grid_x"]
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grid_y = tile_data["grid_y"]
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def add_segment(name, tiles, segtype, frames, words, baseaddr=None):
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assert name not in segments
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segment = segments.setdefault(name, {})
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segment["tiles"] = tiles
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segment["type"] = segtype
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segment["frames"] = frames
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segment["words"] = words
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if baseaddr:
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verbose and print(
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'make_segment: %s baseaddr %s' % (
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name,
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baseaddr,
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))
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segment["baseaddr"] = baseaddr
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for tile_name in tiles:
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database[tile_name]["segment"] = name
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def process_clb():
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if tile_type in ["CLBLL_L", "CLBLM_L"]:
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int_tile_name = tiles_by_grid[(grid_x + 1, grid_y)]
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else:
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int_tile_name = tiles_by_grid[(grid_x - 1, grid_y)]
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add_segment(
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name="SEG_" + tile_name,
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tiles=[tile_name, int_tile_name],
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segtype=tile_type.lower(),
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frames=36,
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words=2,
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baseaddr=tile_baseaddrs.get(tile_name, None))
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def process_hclk():
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add_segment(
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name="SEG_" + tile_name,
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tiles=[tile_name],
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segtype=tile_type.lower(),
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frames=26,
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words=1)
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def process_bram_dsp():
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for k in range(5):
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if tile_type in ["BRAM_L", "DSP_L"]:
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interface_tile_name = tiles_by_grid[(
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grid_x + 1, grid_y - k)]
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int_tile_name = tiles_by_grid[(grid_x + 2, grid_y - k)]
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elif tile_type in ["BRAM_R", "DSP_R"]:
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interface_tile_name = tiles_by_grid[(
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grid_x - 1, grid_y - k)]
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int_tile_name = tiles_by_grid[(grid_x - 2, grid_y - k)]
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else:
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assert 0
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'''
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BRAM/DSP itself is at the base y address
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There is one huge switchbox on the right for the 5 tiles
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These fan into 5 BRAM_INT_INTERFACE tiles each which feed into their own CENTER_INTER (just like a CLB has)
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'''
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if k == 0:
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tiles = [tile_name, interface_tile_name, int_tile_name]
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else:
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tiles = [interface_tile_name, int_tile_name]
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add_segment(
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# BRAM_L_X6Y70 => SEG_BRAM4_L_X6Y70
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name="SEG_" + tile_name.replace("_", "%d_" % k, 1),
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tiles=tiles,
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# BRAM_L => bram4_l
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segtype=tile_type.lower().replace("_", "%d_" % k, 1),
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frames=28,
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words=2)
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def process_default():
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#verbose and nolr(tile_type) not in ('VBRK', 'INT', 'NULL') and print('make_segment: drop %s' % (tile_type,))
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pass
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{
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"CLBLL": process_clb,
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"CLBLM": process_clb,
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"HCLK": process_hclk,
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"BRAM": process_bram_dsp,
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"DSP": process_bram_dsp,
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}.get(nolr(tile_type), process_default)()
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return segments
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def get_inttile(database, segment):
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'''Return interconnect tile for given segment'''
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inttiles = [
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tile for tile in segment["tiles"]
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if database[tile]["type"] in ["INT_L", "INT_R"]
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]
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assert len(inttiles) == 1
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return inttiles[0]
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def seg_base_addr_lr_INT(database, segments, tiles_by_grid, verbose=False):
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'''Populate segment base addresses: L/R along INT column'''
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'''
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Create BRAM base addresses based on nearby CLBs
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ie if we have a BRAM_L, compute as nearby CLB_R base address + offset
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'''
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verbose and print('')
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for segment_name in sorted(segments.keys()):
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segment = segments[segment_name]
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baseaddrs = segment.get("baseaddr", None)
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if not baseaddrs:
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continue
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for block_type, (framebase, wordbase) in sorted(baseaddrs.items()):
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verbose and print(
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'lr_INT: %s: %s.0x%08X:%u' %
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(segment_name, block_type, framebase, wordbase))
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if block_type != 'CLB_IO_CLK':
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verbose and print(' Skip non CLB')
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continue
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inttile = get_inttile(database, segment)
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grid_x = database[inttile]["grid_x"]
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grid_y = database[inttile]["grid_y"]
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if database[inttile]["type"] == "INT_L":
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grid_x += 1
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framebase = framebase + 0x80
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elif database[inttile]["type"] == "INT_R":
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grid_x -= 1
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framebase = framebase - 0x80
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else:
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assert 0
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# ROI at edge?
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if (grid_x, grid_y) not in tiles_by_grid:
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verbose and print(' Skip edge')
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continue
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tile = tiles_by_grid[(grid_x, grid_y)]
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if database[inttile]["type"] == "INT_L":
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assert database[tile]["type"] == "INT_R"
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elif database[inttile]["type"] == "INT_R":
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assert database[tile]["type"] == "INT_L"
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else:
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assert 0
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assert "segment" in database[tile]
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seg = database[tile]["segment"]
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seg_baseaddrs = segments[seg].setdefault("baseaddr", {})
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# At least one duplicate when we re-compute the entry for the base address
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# should give the same address
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if block_type in seg_baseaddrs:
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assert seg_baseaddrs[block_type] == [
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framebase, wordbase
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], (seg_baseaddrs[block_type], [framebase, wordbase])
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verbose and print(' Existing OK')
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else:
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seg_baseaddrs[block_type] = [framebase, wordbase]
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verbose and print(' Add new')
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def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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'''Populate segment base addresses: Up along INT/HCLK columns'''
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verbose and print('')
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'''
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All baseaddrs so far have 50 tiles above them to be derived
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However, once we start deriving, this is no longer true
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Copy the initial list so that any baseaddr encountered can safely be swept up
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'''
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src_segment_names = list()
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for segment_name in segments.keys():
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if "baseaddr" in segments[segment_name]:
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src_segment_names.append(segment_name)
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verbose and print('up_INT: %u base addresses' % len(src_segment_names))
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#verbose and print('\n'.join(sorted(src_segment_names)))
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for src_segment_name in sorted(src_segment_names):
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src_segment = segments[src_segment_name]
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for block_type, (framebase,
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wordbase) in sorted(src_segment["baseaddr"].items()):
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verbose and print(
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'up_INT: %s: %s.0x%08X:%u' %
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(src_segment_name, block_type, framebase, wordbase))
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# Ignore BRAM base addresses
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# TODO: BRAM data needs to be populated in its own special way
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if block_type != 'CLB_IO_CLK':
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verbose and print(' Skip non CLB')
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continue
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inttile = get_inttile(database, src_segment)
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verbose and print(
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' up_INT: %s => inttile %s' % (src_segment_name, inttile))
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grid_x = database[inttile]["grid_x"]
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grid_y = database[inttile]["grid_y"]
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for i in range(50):
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grid_y -= 1
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dst_tile = database[tiles_by_grid[(grid_x, grid_y)]]
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if wordbase == 50:
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wordbase += 1
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else:
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wordbase += 2
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#verbose and print(' dst_tile', dst_tile)
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dst_segment_name = dst_tile["segment"]
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#verbose and print('up_INT: %s => %s' % (src_segment_name, dst_segment_name))
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segments[dst_segment_name].setdefault(
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"baseaddr", {})[block_type] = [framebase, wordbase]
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def add_tile_bits(tile_db, baseaddr, offset, height):
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'''
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Record data structure geometry for the given tile baseaddr
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For most tiles there is only one baseaddr, but some like BRAM have multiple
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Notes on multiple block types:
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https://github.com/SymbiFlow/prjxray/issues/145
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'''
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bits = tile_db.setdefault('bits', {})
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block_type = addr2btype(baseaddr)
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assert block_type not in bits
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block = bits.setdefault(block_type, {})
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block["baseaddr"] = '0x%08X' % baseaddr
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block["offset"] = offset
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block["height"] = height
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def add_bits(database, segments):
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'''Transfer segment data into tiles'''
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for segment_name in segments.keys():
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for _block_type, (
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baseaddr,
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offset) in segments[segment_name]["baseaddr"].items():
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for tile_name in segments[segment_name]["tiles"]:
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tile_type = database[tile_name]["type"]
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height = {
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"CLBLL": 2,
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"CLBLM": 2,
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"INT": 2,
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"HCLK": 1,
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"BRAM": 10,
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"DSP": 10,
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"INT_INTERFACE": 0,
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"BRAM_INT_INTERFACE": 0,
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}.get(nolr(tile_type), None)
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if height is None:
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raise ValueError("Unknown tile type %s" % tile_type)
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if height:
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add_tile_bits(
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database[tile_name], baseaddr, offset, height)
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def annotate_segments(database, segments):
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# TODO: Migrate to new tilegrid format via library. This data is added for
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# compability with unconverted tools. Update tools then remove this data from
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# tilegrid.json.
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for tiledata in database.values():
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if "segment" in tiledata:
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segment = tiledata["segment"]
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tiledata["frames"] = segments[segment]["frames"]
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tiledata["words"] = segments[segment]["words"]
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tiledata["segment_type"] = segments[segment]["type"]
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def run(tiles_fn, json_fn, deltas_fns, verbose=False):
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# Load input files
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tiles = load_tiles(tiles_fn)
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site_baseaddr = load_baseaddrs(deltas_fns)
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# Index input
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database = make_database(tiles)
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tile_baseaddrs = make_tile_baseaddrs(tiles, site_baseaddr, verbose=verbose)
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tiles_by_grid = make_tiles_by_grid(tiles)
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segments = make_segments(
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database, tiles_by_grid, tile_baseaddrs, verbose=verbose)
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# Reference adjacent CLBs to locate adjacent tiles by known offsets
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seg_base_addr_lr_INT(database, segments, tiles_by_grid, verbose=verbose)
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seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=verbose)
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add_bits(database, segments)
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annotate_segments(database, segments)
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#database = {'BRAM_L_X6Y50': database["BRAM_L_X6Y50"]}
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# Save
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json.dump(
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database,
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open(json_fn, 'w'),
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sort_keys=True,
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indent=4,
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separators=(',', ': '))
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def main():
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import argparse
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parser = argparse.ArgumentParser(
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description=
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'Generate a simple wrapper to test synthesizing an arbitrary verilog module'
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)
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parser.add_argument('--verbose', action='store_true', help='')
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parser.add_argument('--out', default='/dev/stdout', help='Output JSON')
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parser.add_argument(
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'--tiles', default='tiles.txt', help='Input tiles.txt tcl output')
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parser.add_argument(
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'deltas', nargs='+', help='.bit diffs to create base addresses from')
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args = parser.parse_args()
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run(args.tiles, args.out, args.deltas, verbose=args.verbose)
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if __name__ == '__main__':
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main()
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