mirror of https://github.com/openXC7/prjxray.git
37 lines
738 B
Verilog
37 lines
738 B
Verilog
// Copyright (C) 2017-2020 The Project X-Ray Authors.
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//
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// Use of this source code is governed by a ISC-style
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// license that can be found in the LICENSE file or at
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// https://opensource.org/licenses/ISC
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//
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// SPDX-License-Identifier: ISC
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`default_nettype none
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// ============================================================================
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module lfsr #
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(
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parameter WIDTH = 16,
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parameter [WIDTH-1:0] POLY = 16'hD008,
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parameter [WIDTH-1:0] SEED = 1
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)
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(
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input wire clk,
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input wire rst,
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input wire ce,
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output reg [WIDTH-1:0] r
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);
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wire feedback = ^(r & POLY);
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always @(posedge clk) begin
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if(rst) begin
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r <= SEED;
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end else if(ce) begin
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r <= {r[WIDTH-2:0], feedback};
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end
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end
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endmodule
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