mirror of https://github.com/openXC7/prjxray.git
79 lines
1.4 KiB
Verilog
79 lines
1.4 KiB
Verilog
// Copyright (C) 2017-2020 The Project X-Ray Authors.
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//
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// Use of this source code is governed by a ISC-style
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// license that can be found in the LICENSE file or at
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// https://opensource.org/licenses/ISC
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//
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// SPDX-License-Identifier: ISC
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`default_nettype none
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`timescale 1ns / 1ps
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`include "../src/message_formatter.v"
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// ============================================================================
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module tb;
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// ============================================================================
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reg CLK;
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initial CLK <= 1'b0;
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always #0.5 CLK <= !CLK;
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reg [3:0] rst_sr;
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initial rst_sr <= 4'hF;
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always @(posedge CLK) rst_sr <= rst_sr >> 1;
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wire RST;
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assign RST = rst_sr[0];
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// ============================================================================
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initial begin
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$dumpfile("waveforms.vcd");
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$dumpvars;
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end
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integer cycle_cnt;
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initial cycle_cnt <= 0;
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always @(posedge CLK)
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if (!RST) cycle_cnt <= cycle_cnt + 1;
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always @(posedge CLK)
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if (!RST && cycle_cnt >= 150)
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$finish;
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// ============================================================================
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wire i_stb = (cycle_cnt == 10);
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wire [32*2-1:0] i_dat = 64'h01234567_ABCD4321;
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wire o_stb;
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wire [7:0] o_dat;
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message_formatter #
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(
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.WIDTH (32),
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.COUNT (2),
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.TX_INTERVAL (4)
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)
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dut
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(
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.CLK (CLK),
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.RST (RST),
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.I_STB (i_stb),
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.I_DAT (i_dat),
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.O_STB (o_stb),
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.O_DAT (o_dat)
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);
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always @(posedge CLK)
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if (o_stb)
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$display("%c", o_dat);
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endmodule
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