mirror of https://github.com/openXC7/prjxray.git
186 lines
3.6 KiB
Verilog
186 lines
3.6 KiB
Verilog
// Copyright (C) 2017-2020 The Project X-Ray Authors.
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//
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// Use of this source code is governed by a ISC-style
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// license that can be found in the LICENSE file or at
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// https://opensource.org/licenses/ISC
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//
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// SPDX-License-Identifier: ISC
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`include "src/idelay_calibrator.v"
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`default_nettype none
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// ============================================================================
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module top
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(
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input wire clk,
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input wire rx,
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output wire tx,
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input wire [15:0] sw,
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output wire [15:0] led,
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input wire ja1,
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input wire ja2,
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input wire ja3,
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input wire ja4,
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input wire ja7,
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input wire ja8,
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input wire ja9,
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input wire ja10,
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input wire jb1,
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input wire jb2,
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input wire jb3,
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input wire jb4,
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input wire jb7,
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input wire jb8,
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input wire jb9,
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input wire jb10,
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input wire jc1,
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input wire jc2,
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input wire jc3,
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input wire jc4,
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input wire jc7,
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input wire jc8,
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input wire jc9,
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input wire jc10,
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output wire xadc1_p,
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output wire xadc2_p,
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input wire xadc3_p,
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input wire xadc4_p,
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input wire xadc1_n,
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output wire xadc2_n,
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input wire xadc3_n,
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input wire xadc4_n
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);
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// ============================================================================
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// Clock & reset
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reg [3:0] rst_sr;
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initial rst_sr <= 4'hF;
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always @(posedge clk)
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if (sw[0])
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rst_sr <= 4'hF;
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else
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rst_sr <= rst_sr >> 1;
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wire CLK = clk;
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wire RST = rst_sr[0];
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// ============================================================================
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// IDELAY calibrator
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wire cal_rdy;
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idelay_calibrator cal
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(
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.refclk (CLK),
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.rst (RST),
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.rdy (cal_rdy)
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);
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// ============================================================================
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// Delay selector
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wire btn_in = sw[1];
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reg [3:0] btn_sr;
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wire btn_edge;
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reg [16:0] btn_cnt;
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always @(posedge CLK)
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if (RST)
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btn_sr <= (btn_in) ? 4'hF : 4'h0;
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else
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btn_sr <= (btn_sr >> 1) | (btn_in << 3);
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assign btn_edge = btn_sr[1] ^ btn_sr[0];
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always @(posedge CLK)
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if (RST)
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btn_cnt <= -1;
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else if (btn_edge)
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btn_cnt <= 1000000 - 1;
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else if (!btn_cnt[15])
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btn_cnt <= btn_cnt - 1;
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wire dly_ld_req = btn_edge && btn_cnt[15];
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// ============================================================================
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// IDELAY path
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reg dly_ld;
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wire dly_out;
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reg [4:0] dly_delay_in;
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wire [4:0] dly_delay_out;
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always @(posedge CLK)
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if (RST || !cal_rdy)
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dly_ld <= 0;
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else if ( dly_ld)
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dly_ld <= 0;
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else if (!dly_ld && dly_ld_req)
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dly_ld <= 1;
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always @(posedge CLK)
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if (RST || !cal_rdy)
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dly_delay_in <= 0;
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else if (!dly_ld && dly_ld_req)
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dly_delay_in <= dly_delay_in + 1;
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(* KEEP, DONT_TOUCH *)
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IDELAYE2 #
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(
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.IDELAY_TYPE ("VAR_LOAD"),
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.DELAY_SRC ("IDATAIN")
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)
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idelay
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(
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.IDATAIN (xadc1_n),
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.DATAOUT (dly_out),
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.REGRST (RST),
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.C (CLK),
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.LD (dly_ld),
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.CNTVALUEIN (dly_delay_in),
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.CNTVALUEOUT (dly_delay_out)
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);
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// ============================================================================
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// I/O connections
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reg O;
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always @(posedge CLK)
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if (RST) O <= 0;
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else O <= ~O;
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reg [23:0] heartbeat_cnt;
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always @(posedge CLK)
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heartbeat_cnt <= heartbeat_cnt + 1;
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assign led[ 0] = heartbeat_cnt[23];
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assign led[ 1] = cal_rdy;
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assign led[ 2] = 1'b0;
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assign led[ 3] = 1'b0;
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assign led[ 4] = 1'b0;
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assign led[ 5] = 1'b0;
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assign led[ 6] = 1'b0;
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assign led[ 7] = 1'b0;
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assign led[ 8] = 1'b0;
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assign led[ 9] = 1'b0;
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assign led[10] = 1'b0;
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assign led[11] = dly_delay_out[0];
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assign led[12] = dly_delay_out[1];
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assign led[13] = dly_delay_out[2];
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assign led[14] = dly_delay_out[3];
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assign led[15] = dly_delay_out[4];
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assign xadc2_p = O;
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assign xadc2_n = O;
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assign xadc1_p = dly_out;
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endmodule
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