mirror of https://github.com/openXC7/prjxray.git
176 lines
3.4 KiB
Verilog
176 lines
3.4 KiB
Verilog
// Copyright (C) 2017-2020 The Project X-Ray Authors.
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//
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// Use of this source code is governed by a ISC-style
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// license that can be found in the LICENSE file or at
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// https://opensource.org/licenses/ISC
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//
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// SPDX-License-Identifier: ISC
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`include "src/idelay_calibrator.v"
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`default_nettype none
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// ============================================================================
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module top
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(
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input wire clk,
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input wire rx,
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output wire tx,
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input wire [15:0] sw,
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output wire [15:0] led,
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output wire ja1,
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output wire ja2,
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output wire ja3,
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output wire ja4,
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output wire ja7,
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output wire ja8,
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output wire ja9,
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output wire ja10,
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output wire jb1,
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output wire jb2,
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output wire jb3,
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output wire jb4,
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output wire jb7,
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output wire jb8,
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output wire jb9,
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output wire jb10,
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output wire jc1,
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output wire jc2,
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output wire jc3,
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output wire jc4,
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output wire jc7,
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output wire jc8,
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output wire jc9,
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output wire jc10,
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output wire xadc1_p,
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output wire xadc2_p,
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output wire xadc3_p,
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output wire xadc4_p,
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output wire xadc1_n,
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output wire xadc2_n,
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output wire xadc3_n,
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output wire xadc4_n
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);
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// ============================================================================
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// Clock & reset
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reg [3:0] rst_sr;
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initial rst_sr <= 4'hF;
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always @(posedge clk)
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if (sw[0])
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rst_sr <= 4'hF;
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else
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rst_sr <= rst_sr >> 1;
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wire CLK = clk;
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wire RST = rst_sr[0];
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// ============================================================================
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// IDELAY calibrator
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wire cal_rdy;
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idelay_calibrator cal
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(
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.refclk (CLK),
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.rst (RST),
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.rdy (cal_rdy)
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);
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// ============================================================================
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reg dly_in;
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wire [31:0] dly_out;
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always @(posedge CLK)
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if (RST) dly_in <= 0;
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else dly_in <= ~dly_in;
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genvar i;
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generate for (i=0; i<32; i=i+1) begin
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(* KEEP, DONT_TOUCH *)
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IDELAYE2 #
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(
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.IDELAY_TYPE ("FIXED"),
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.IDELAY_VALUE (i),
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.DELAY_SRC ("DATAIN")
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)
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idelay
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(
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.DATAIN (dly_in),
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.DATAOUT (dly_out[i])
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);
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end endgenerate
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// ============================================================================
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// I/O connections
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reg [23:0] heartbeat_cnt;
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always @(posedge CLK)
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heartbeat_cnt <= heartbeat_cnt + 1;
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assign led[ 0] = heartbeat_cnt[23];
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assign led[ 1] = cal_rdy;
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assign led[ 2] = 1'b0;
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assign led[ 3] = 1'b0;
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assign led[ 4] = 1'b0;
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assign led[ 5] = 1'b0;
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assign led[ 6] = 1'b0;
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assign led[ 7] = 1'b0;
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assign led[ 8] = 1'b0;
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assign led[ 9] = 1'b0;
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assign led[10] = 1'b0;
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assign led[11] = 1'b0;
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assign led[12] = 1'b0;
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assign led[13] = 1'b0;
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assign led[14] = 1'b0;
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assign led[15] = 1'b0;
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assign ja1 = dly_out[ 0];
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assign ja2 = dly_out[ 1];
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assign ja3 = dly_out[ 2];
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assign ja4 = dly_out[ 3];
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assign ja7 = dly_out[ 4];
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assign ja8 = dly_out[ 5];
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assign ja9 = dly_out[ 6];
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assign ja10 = dly_out[ 7];
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assign jb1 = dly_out[ 8];
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assign jb2 = dly_out[ 9];
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assign jb3 = dly_out[10];
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assign jb4 = dly_out[11];
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assign jb7 = dly_out[12];
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assign jb8 = dly_out[13];
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assign jb9 = dly_out[14];
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assign jb10 = dly_out[15];
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assign jc1 = dly_out[16];
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assign jc2 = dly_out[17];
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assign jc3 = dly_out[18];
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assign jc4 = dly_out[19];
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assign jc7 = dly_out[20];
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assign jc8 = dly_out[21];
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assign jc9 = dly_out[22];
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assign jc10 = dly_out[23];
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assign xadc1_p = dly_out[24];
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assign xadc2_p = dly_out[25];
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assign xadc3_p = dly_out[26];
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assign xadc4_p = dly_out[27];
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assign xadc1_n = dly_out[28];
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assign xadc2_n = dly_out[29];
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assign xadc3_n = dly_out[30];
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assign xadc4_n = dly_out[31];
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endmodule
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