mirror of https://github.com/openXC7/prjxray.git
52 lines
1.2 KiB
Python
52 lines
1.2 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import json
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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def main():
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segmk = Segmaker("design.bits")
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print("Loading tags")
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with open('params.json') as f:
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params = json.load(f)
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for row in params:
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base_name = 'BUFHCE_X{}Y{}'.format(row['x'], row['y'])
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segmk.add_site_tag(
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row['site'], '{}.IN_USE'.format(base_name), row['IN_USE'])
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if not row['IN_USE']:
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continue
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segmk.add_site_tag(
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row['site'], '{}.INIT_OUT'.format(base_name), row['INIT_OUT'])
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segmk.add_site_tag(
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row['site'], '{}.ZINV_CE'.format(base_name),
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1 ^ row['IS_CE_INVERTED'])
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# SYNC is a zero pattern
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for opt in ['ASYNC']:
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segmk.add_site_tag(
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row['site'], '{}.CE_TYPE.'.format(base_name) + opt,
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verilog.unquote(row['CE_TYPE']) == opt)
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segmk.compile()
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segmk.write()
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if __name__ == '__main__':
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main()
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