mirror of https://github.com/openXC7/prjxray.git
442 lines
12 KiB
Python
442 lines
12 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import json
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import io
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import lut_maker
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from prjxray import verilog
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from prjxray.db import Database
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def gen_sites():
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'''
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IOB33S: main IOB of a diff pair
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IOB33M: secondary IOB of a diff pair
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IOB33: not a diff pair. Relatively rare (at least in ROI...2 of them?)
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Focus on IOB33S to start
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'''
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['IOB33S', 'IOB33M']:
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yield tile_name, site_name
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def write_params(params):
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pinstr = 'tile,site,pin,iostandard,drive,slew\n'
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for vals in params:
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pinstr += ','.join(map(str, vals)) + '\n'
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open('params.csv', 'w').write(pinstr)
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def use_oserdese2(p, luts, connects):
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p['oddr_mux_config'] = 'none'
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p['tddr_mux_config'] = 'none'
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p['DATA_RATE_OQ'] = verilog.quote(random.choice((
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'SDR',
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'DDR',
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)))
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p['DATA_RATE_TQ'] = verilog.quote(random.choice((
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'BUF',
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'SDR',
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'DDR',
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)))
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if verilog.unquote(p['DATA_RATE_OQ']) == 'SDR':
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data_widths = [2, 3, 4, 5, 6, 7, 8]
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else:
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data_widths = [4, 6, 8]
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p['DATA_WIDTH'] = random.choice(data_widths)
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if p['DATA_WIDTH'] == 4 and verilog.unquote(
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p['DATA_RATE_OQ']) == 'DDR' and verilog.unquote(
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p['DATA_RATE_TQ']) == 'DDR':
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tristate_width = 4
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else:
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tristate_width = 1
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p['SERDES_MODE'] = verilog.quote(random.choice(('MASTER', 'SLAVE')))
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p['TRISTATE_WIDTH'] = tristate_width
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p['OSERDES_MODE'] = verilog.quote(random.choice(('MASTER', 'SLAVE')))
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if p['io']:
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p['TFB'] = '.TFB(tfb_{site}),'.format(**p)
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p['TQ'] = '.TQ({twire}),'.format(**p)
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p['t1net'] = luts.get_next_output_net()
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p['t2net'] = luts.get_next_output_net()
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p['t3net'] = luts.get_next_output_net()
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p['t4net'] = luts.get_next_output_net()
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p['tcenet'] = luts.get_next_output_net()
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for idx in range(4):
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p['IS_T{}_INVERTED'.format(idx + 1)] = random.randint(0, 1)
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else:
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p['TFB'] = '.TFB(),'
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p['TQ'] = '.TQ(),'
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p['t1net'] = ''
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p['t2net'] = ''
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p['t3net'] = ''
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p['t4net'] = ''
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p['tcenet'] = ''
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for idx in range(4):
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p['IS_T{}_INVERTED'.format(idx + 1)] = 0
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p['SRVAL_OQ'] = random.randint(0, 1)
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p['SRVAL_TQ'] = random.randint(0, 1)
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p['INIT_OQ'] = random.randint(0, 1)
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p['INIT_TQ'] = random.randint(0, 1)
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for idx in range(8):
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p['IS_D{}_INVERTED'.format(idx + 1)] = random.randint(0, 1)
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p['IS_CLK_INVERTED'] = random.randint(0, 1)
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p['IS_CLKDIV_INVERTED'] = random.randint(0, 1)
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clk_connections = ''
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p['CLK_USED'] = random.randint(0, 1)
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p['CLKDIV_USED'] = random.randint(0, 1)
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if p['CLK_USED']:
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clk_connections += '''
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.CLK({}),'''.format(luts.get_next_output_net())
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if p['CLKDIV_USED']:
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clk_connections += '''
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.CLKDIV({}),'''.format(luts.get_next_output_net())
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *)
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OSERDESE2 #(
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.SERDES_MODE({OSERDES_MODE}),
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.DATA_RATE_TQ({DATA_RATE_TQ}),
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.DATA_RATE_OQ({DATA_RATE_OQ}),
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.DATA_WIDTH({DATA_WIDTH}),
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.TRISTATE_WIDTH({TRISTATE_WIDTH}),
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.SRVAL_OQ({SRVAL_OQ}),
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.SRVAL_TQ({SRVAL_TQ}),
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.INIT_OQ({INIT_OQ}),
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.INIT_TQ({INIT_TQ}),
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.IS_T1_INVERTED({IS_T1_INVERTED}),
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.IS_T2_INVERTED({IS_T2_INVERTED}),
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.IS_T3_INVERTED({IS_T3_INVERTED}),
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.IS_T4_INVERTED({IS_T4_INVERTED}),
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.IS_D1_INVERTED({IS_D1_INVERTED}),
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.IS_D2_INVERTED({IS_D2_INVERTED}),
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.IS_D3_INVERTED({IS_D3_INVERTED}),
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.IS_D4_INVERTED({IS_D4_INVERTED}),
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.IS_D5_INVERTED({IS_D5_INVERTED}),
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.IS_D6_INVERTED({IS_D6_INVERTED}),
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.IS_D7_INVERTED({IS_D7_INVERTED}),
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.IS_D8_INVERTED({IS_D8_INVERTED}),
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.IS_CLK_INVERTED({IS_CLK_INVERTED}),
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.IS_CLKDIV_INVERTED({IS_CLKDIV_INVERTED})
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) oserdese2_{site} (
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.OQ({owire}),
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{TFB}
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{TQ}
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{clk_connections}
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.D1({d1net}),
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.D2({d2net}),
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.D3({d3net}),
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.D4({d4net}),
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.D5({d5net}),
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.D6({d6net}),
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.D7({d7net}),
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.D8({d8net}),
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.OCE({ocenet}),
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.RST({rstnet}),
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.T1({t1net}),
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.T2({t2net}),
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.T3({t3net}),
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.T4({t4net}),
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.TCE({tcenet})
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);'''.format(
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clk_connections=clk_connections,
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rstnet=luts.get_next_output_net(),
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d1net=luts.get_next_output_net(),
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d2net=luts.get_next_output_net(),
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d3net=luts.get_next_output_net(),
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d4net=luts.get_next_output_net(),
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d5net=luts.get_next_output_net(),
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d6net=luts.get_next_output_net(),
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d7net=luts.get_next_output_net(),
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d8net=luts.get_next_output_net(),
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ocenet=luts.get_next_output_net(),
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ofb_wire=luts.get_next_input_net(),
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**p),
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file=connects)
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def use_direct_and_oddr(p, luts, connects):
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p['oddr_mux_config'] = random.choice((
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'direct',
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'lut',
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'none',
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))
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if p['io']:
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if p['oddr_mux_config'] != 'lut':
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p['tddr_mux_config'] = random.choice((
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'direct',
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'lut',
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'none',
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))
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else:
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p['tddr_mux_config'] = random.choice((
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'lut',
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'none',
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))
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else:
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p['tddr_mux_config'] = 'none'
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# toddr and oddr share the same clk
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clknet = luts.get_next_output_net()
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p['IS_CLK_INVERTED'] = 0
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if p['tddr_mux_config'] == 'direct':
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p['TINIT'] = random.randint(0, 1)
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p['TSRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC')))
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p['TDDR_CLK_EDGE'] = verilog.quote('OPPOSITE_EDGE')
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# Note: it seems that CLK_EDGE setting is ignored for TDDR
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p['TDDR_CLK_EDGE'] = verilog.quote(
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random.choice(('OPPOSITE_EDGE', 'SAME_EDGE')))
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *)
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ODDR #(
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.INIT({TINIT}),
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.SRTYPE({TSRTYPE}),
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.DDR_CLK_EDGE({TDDR_CLK_EDGE}),
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.IS_C_INVERTED({IS_CLK_INVERTED})
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) toddr_{site} (
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.C({cnet}),
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.D1({d1net}),
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.D2({d2net}),
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.CE({cenet}),
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.Q(tddr_d_{site})
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);
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'''.format(
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cnet=clknet,
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d1net=luts.get_next_output_net(),
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d2net=luts.get_next_output_net(),
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cenet=luts.get_next_output_net(),
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**p),
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file=connects)
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if p['tddr_mux_config'] == 'direct':
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print(
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'''
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assign {twire} = tddr_d_{site};'''.format(**p, ),
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file=connects)
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elif p['tddr_mux_config'] == 'lut':
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print(
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'''
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assign {twire} = {lut};'''.format(lut=luts.get_next_output_net(), **p),
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file=connects)
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pass
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elif p['tddr_mux_config'] == 'none':
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pass
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else:
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assert False, p['tddr_mux_config']
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if p['oddr_mux_config'] == 'direct':
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p['QINIT'] = random.randint(0, 1)
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p['SRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC')))
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p['ODDR_CLK_EDGE'] = verilog.quote(
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random.choice((
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'OPPOSITE_EDGE',
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'SAME_EDGE',
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)))
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *)
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ODDR #(
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.INIT({QINIT}),
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.SRTYPE({SRTYPE}),
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.DDR_CLK_EDGE({ODDR_CLK_EDGE}),
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.IS_C_INVERTED({IS_CLK_INVERTED})
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) oddr_{site} (
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.C({cnet}),
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.D1({d1net}),
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.D2({d2net}),
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.CE({cenet}),
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.Q(oddr_d_{site})
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);
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'''.format(
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cnet=clknet,
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d1net=luts.get_next_output_net(),
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d2net=luts.get_next_output_net(),
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cenet=luts.get_next_output_net(),
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**p),
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file=connects)
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if p['oddr_mux_config'] == 'direct':
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print(
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'''
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assign {owire} = oddr_d_{site};'''.format(**p, ),
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file=connects)
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elif p['oddr_mux_config'] == 'lut':
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print(
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'''
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assign {owire} = {lut};'''.format(lut=luts.get_next_output_net(), **p),
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file=connects)
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pass
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elif p['oddr_mux_config'] == 'none':
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pass
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else:
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assert False, p['oddr_mux_config']
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def run():
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iostandards = [
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'LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL'
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]
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iostandard = random.choice(iostandards)
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if iostandard in ['LVTTL', 'LVCMOS18']:
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drives = [4, 8, 12, 16, 24]
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elif iostandard == 'LVCMOS12':
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drives = [4, 8, 12]
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else:
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drives = [4, 8, 12, 16]
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slews = ['FAST', 'SLOW']
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pulls = ["NONE", "KEEPER", "PULLDOWN", "PULLUP"]
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luts = lut_maker.LutMaker()
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connects = io.StringIO()
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tile_params = []
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params = []
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ndio = 0
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ndo = 0
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for idx, (tile, site) in enumerate(gen_sites()):
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if idx == 0:
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continue
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p = {}
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p['tile'] = tile
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p['site'] = site
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p['ilogic_loc'] = site.replace('IOB', 'ILOGIC')
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p['ologic_loc'] = site.replace('IOB', 'OLOGIC')
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p['IOSTANDARD'] = verilog.quote(iostandard)
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p['PULLTYPE'] = verilog.quote(random.choice(pulls))
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p['DRIVE'] = random.choice(drives)
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p['SLEW'] = verilog.quote(random.choice(slews))
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p['io'] = random.randint(0, 1)
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p['owire'] = 'do_buf[{}]'.format(idx - 1)
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if p['io']:
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p['pad_wire'] = 'dio[{}]'.format(ndio)
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ndio += 1
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p['iwire'] = 'di_buf[{}]'.format(idx - 1)
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p['twire'] = 't[{}]'.format(idx - 1)
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else:
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p['pad_wire'] = 'do[{}]'.format(ndo)
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ndo += 1
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params.append(p)
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tile_params.append(
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(
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tile, site, p['pad_wire'], iostandard, p['DRIVE'],
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verilog.unquote(p['SLEW']) if p['SLEW'] else None,
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verilog.unquote(p['PULLTYPE'])))
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write_params(tile_params)
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print(
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'''
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`define N_DO {n_do}
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`define N_DIO {n_dio}
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module top(input clk, output wire [`N_DO-1:0] do, inout wire [`N_DIO-1:0] dio);
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wire [(`N_DIO+`N_DO)-1:0] di_buf;
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wire [(`N_DIO+`N_DO)-1:0] do_buf;
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wire [(`N_DIO+`N_DO)-1:0] t;
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'''.format(n_dio=ndio, n_do=ndo))
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# Always output a LUT6 to make placer happy.
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print(
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'''
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(* KEEP, DONT_TOUCH *)
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LUT6 dummy_lut();
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''')
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for p in params:
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if p['io']:
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print(
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'''
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wire oddr_d_{site};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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IOBUF #(
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.IOSTANDARD({IOSTANDARD})
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) obuf_{site} (
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.IO({pad_wire}),
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.I({owire}),
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.O({iwire}),
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.T({twire})
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);
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'''.format(**p),
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file=connects)
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else:
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print(
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'''
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wire oddr_d_{site};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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OBUF #(
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.IOSTANDARD({IOSTANDARD})
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) obuf_{site} (
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.O({pad_wire}),
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.I({owire})
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);
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'''.format(**p),
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file=connects)
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p['use_oserdese2'] = random.randint(0, 1)
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if p['use_oserdese2']:
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use_oserdese2(p, luts, connects)
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else:
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use_direct_and_oddr(p, luts, connects)
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for l in luts.create_wires_and_luts():
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print(l)
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print(connects.getvalue())
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print("endmodule")
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with open('params.jl', 'w') as f:
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json.dump(params, f, indent=2)
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if __name__ == '__main__':
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run()
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